| Tianrui Wei | 2ef594d | 2021-07-01 12:54:19 +0800 | [diff] [blame] | 1 | if TARGET_OPENPITON_RISCV64 |
| 2 | |
| 3 | config SYS_BOARD |
| 4 | default "riscv64" |
| 5 | |
| 6 | config SYS_VENDOR |
| 7 | default "openpiton" |
| 8 | |
| 9 | config SYS_CPU |
| 10 | default "generic" |
| 11 | |
| 12 | config SYS_CONFIG_NAME |
| 13 | default "openpiton-riscv64" |
| 14 | |
| Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 15 | config TEXT_BASE |
| Tianrui Wei | 2ef594d | 2021-07-01 12:54:19 +0800 | [diff] [blame] | 16 | default 0x81000000 if SPL |
| 17 | default 0x80000000 if !RISCV_SMODE |
| 18 | default 0x81000000 if RISCV_SMODE |
| 19 | |
| 20 | config SPL_TEXT_BASE |
| 21 | default 0x82000000 |
| 22 | |
| 23 | config SPL_OPENSBI_LOAD_ADDR |
| 24 | default 0x80000000 |
| 25 | |
| 26 | config BOARD_SPECIFIC_OPTIONS # dummy |
| 27 | def_bool y |
| 28 | select ARCH_EARLY_INIT_R |
| 29 | select SUPPORT_SPL |
| 30 | imply CPU_RISCV |
| 31 | imply RISCV_TIMER |
| Bin Meng | b5f0372 | 2023-06-21 23:11:46 +0800 | [diff] [blame] | 32 | imply SPL_RISCV_ACLINT |
| Tianrui Wei | 2ef594d | 2021-07-01 12:54:19 +0800 | [diff] [blame] | 33 | imply CMD_CPU |
| 34 | imply SPL_CPU_SUPPORT |
| 35 | imply SPL_SMP |
| 36 | imply SPL_MMC |
| 37 | imply SMP |
| 38 | imply SPL_RISCV_MMODE |
| 39 | |
| 40 | endif |