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git01.mediatek.com / filogic / uboot / 5a85d05558dd6f7411632916155b123773ac31a9 / . / drivers / clk / starfive / clk-jh7110.c
blob: a74b70906a6e871ca6cc9d128c08a2bcf0ef299e [file] [log] [blame]
Yanhong Wang5a85d052023-03-29 11:42:13 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022-23 StarFive Technology Co., Ltd.
4 *
5 * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
6 */
7
8#include <common.h>
9#include <clk.h>
10#include <clk-uclass.h>
11#include <dm.h>
12#include <dm/device.h>
13#include <dm/devres.h>
14#include <dm/lists.h>
15#include <dt-bindings/clock/starfive,jh7110-crg.h>
16#include <log.h>
17#include <linux/clk-provider.h>
18
19#include "clk.h"
20
21#define STARFIVE_CLK_ENABLE_SHIFT 31 /* [31] */
22#define STARFIVE_CLK_INVERT_SHIFT 30 /* [30] */
23#define STARFIVE_CLK_MUX_SHIFT 24 /* [29:24] */
24#define STARFIVE_CLK_DIV_SHIFT 0 /* [23:0] */
25
26#define OFFSET(id) ((id) * 4)
27#define AONOFFSET(id) (((id) - JH7110_SYSCLK_END) * 4)
28#define STGOFFSET(id) (((id) - JH7110_AONCLK_END) * 4)
29
30typedef int (*jh1710_init_fn)(struct udevice *dev);
31
32struct jh7110_clk_priv {
33 void __iomem *reg;
34 jh1710_init_fn init;
35};
36
37static const char *cpu_root_sels[2] = {
38 [0] = "oscillator",
39 [1] = "pll0_out",
40};
41
42static const char *perh_root_sels[2] = {
43 [0] = "pll0_out",
44 [1] = "pll2_out",
45};
46
47static const char *bus_root_sels[2] = {
48 [0] = "oscillator",
49 [1] = "pll2_out",
50};
51
52static const char *qspi_ref_sels[2] = {
53 [0] = "oscillator",
54 [1] = "qspi_ref_src",
55};
56
57static const char *gmac1_tx_sels[2] = {
58 [0] = "gmac1_gtxclk",
59 [1] = "gmac1_rmii_rtx",
60};
61
62static const char *gmac0_tx_sels[2] = {
63 [0] = "gmac0_gtxclk",
64 [1] = "gmac0_rmii_rtx",
65};
66
67static const char *apb_func_sels[2] = {
68 [0] = "osc_div4",
69 [1] = "oscillator",
70};
71
72static const char *gmac1_rx_sels[2] = {
73 [0] = "gmac1-rgmii-rxin-clock",
74 [1] = "gmac1_rmii_rtx",
75};
76
77static struct clk *starfive_clk_mux(void __iomem *reg,
78 const char *name,
79 unsigned int offset,
80 u8 width,
81 const char * const *parent_names,
82 u8 num_parents)
83{
84 return clk_register_mux(NULL, name, parent_names, num_parents, 0,
85 reg + offset, STARFIVE_CLK_MUX_SHIFT,
86 width, 0);
87}
88
89static struct clk *starfive_clk_gate(void __iomem *reg,
90 const char *name,
91 const char *parent_name,
92 unsigned int offset)
93{
94 return clk_register_gate(NULL, name, parent_name, 0, reg + offset,
95 STARFIVE_CLK_ENABLE_SHIFT, 0, NULL);
96}
97
98static struct clk *starfive_clk_inv(void __iomem *reg,
99 const char *name,
100 const char *parent_name,
101 unsigned int offset)
102{
103 return clk_register_gate(NULL, name, parent_name, 0, reg + offset,
104 STARFIVE_CLK_INVERT_SHIFT, 0, NULL);
105}
106
107static struct clk *starfive_clk_divider(void __iomem *reg,
108 const char *name,
109 const char *parent_name,
110 unsigned int offset,
111 u8 width)
112{
113 return clk_register_divider(NULL, name, parent_name, 0, reg + offset,
114 0, width, CLK_DIVIDER_ONE_BASED);
115}
116
117static struct clk *starfive_clk_composite(void __iomem *reg,
118 const char *name,
119 const char * const *parent_names,
120 unsigned int num_parents,
121 unsigned int offset,
122 unsigned int mux_width,
123 unsigned int gate_width,
124 unsigned int div_width)
125{
126 struct clk *clk = ERR_PTR(-ENOMEM);
127 struct clk_divider *div = NULL;
128 struct clk_gate *gate = NULL;
129 struct clk_mux *mux = NULL;
130 int mask_arry[4] = {0x1, 0x3, 0x7, 0xF};
131 int mask;
132
133 if (mux_width) {
134 if (mux_width > 4)
135 goto fail;
136 else
137 mask = mask_arry[mux_width - 1];
138
139 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
140 if (!mux)
141 goto fail;
142
143 mux->reg = reg + offset;
144 mux->mask = mask;
145 mux->shift = STARFIVE_CLK_MUX_SHIFT;
146 mux->num_parents = num_parents;
147 mux->flags = 0;
148 mux->parent_names = parent_names;
149 }
150
151 if (gate_width) {
152 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
153
154 if (!gate)
155 goto fail;
156
157 gate->reg = reg + offset;
158 gate->bit_idx = STARFIVE_CLK_ENABLE_SHIFT;
159 gate->flags = 0;
160 }
161
162 if (div_width) {
163 div = kzalloc(sizeof(*div), GFP_KERNEL);
164 if (!div)
165 goto fail;
166
167 div->reg = reg + offset;
168
169 if (offset == OFFSET(JH7110_SYSCLK_UART3_CORE) ||
170 offset == OFFSET(JH7110_SYSCLK_UART4_CORE) ||
171 offset == OFFSET(JH7110_SYSCLK_UART5_CORE)) {
172 div->shift = 8;
173 div->width = 8;
174 } else {
175 div->shift = STARFIVE_CLK_DIV_SHIFT;
176 div->width = div_width;
177 }
178 div->flags = CLK_DIVIDER_ONE_BASED;
179 div->table = NULL;
180 }
181
182 clk = clk_register_composite(NULL, name,
183 parent_names, num_parents,
184 &mux->clk, &clk_mux_ops,
185 &div->clk, &clk_divider_ops,
186 &gate->clk, &clk_gate_ops, 0);
187
188 if (IS_ERR(clk))
189 goto fail;
190
191 return clk;
192
193fail:
194 kfree(gate);
195 kfree(div);
196 kfree(mux);
197 return ERR_CAST(clk);
198}
199
200static struct clk *starfive_clk_fix_parent_composite(void __iomem *reg,
201 const char *name,
202 const char *parent_names,
203 unsigned int offset,
204 unsigned int mux_width,
205 unsigned int gate_width,
206 unsigned int div_width)
207{
208 const char * const *parents;
209
210 parents = &parent_names;
211
212 return starfive_clk_composite(reg, name, parents, 1, offset,
213 mux_width, gate_width, div_width);
214}
215
216static struct clk *starfive_clk_gate_divider(void __iomem *reg,
217 const char *name,
218 const char *parent,
219 unsigned int offset,
220 unsigned int width)
221{
222 const char * const *parent_names;
223
224 parent_names = &parent;
225
226 return starfive_clk_composite(reg, name, parent_names, 1,
227 offset, 0, 1, width);
228}
229
230static int jh7110_syscrg_init(struct udevice *dev)
231{
232 struct jh7110_clk_priv *priv = dev_get_priv(dev);
233 struct ofnode_phandle_args args;
234 fdt_addr_t addr;
235 struct clk *pclk;
236 int ret;
237
238 ret = ofnode_parse_phandle_with_args(dev->node_, "starfive,sys-syscon", NULL, 0, 0, &args);
239 if (ret)
240 return ret;
241
242 addr = ofnode_get_addr(args.node);
243 if (addr == FDT_ADDR_T_NONE)
244 return -EINVAL;
245
246 clk_dm(JH7110_SYSCLK_PLL0_OUT,
247 starfive_jh7110_pll("pll0_out", "oscillator", (void __iomem *)addr,
248 priv->reg, &starfive_jh7110_pll0));
249 clk_dm(JH7110_SYSCLK_PLL1_OUT,
250 starfive_jh7110_pll("pll1_out", "oscillator", (void __iomem *)addr,
251 priv->reg, &starfive_jh7110_pll1));
252 clk_dm(JH7110_SYSCLK_PLL2_OUT,
253 starfive_jh7110_pll("pll2_out", "oscillator", (void __iomem *)addr,
254 priv->reg, &starfive_jh7110_pll2));
255 clk_dm(JH7110_SYSCLK_CPU_ROOT,
256 starfive_clk_mux(priv->reg, "cpu_root",
257 OFFSET(JH7110_SYSCLK_CPU_ROOT), 1,
258 cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
259 clk_dm(JH7110_SYSCLK_CPU_CORE,
260 starfive_clk_divider(priv->reg,
261 "cpu_core", "cpu_root",
262 OFFSET(JH7110_SYSCLK_CPU_CORE), 3));
263 clk_dm(JH7110_SYSCLK_CPU_BUS,
264 starfive_clk_divider(priv->reg,
265 "cpu_bus", "cpu_core",
266 OFFSET(JH7110_SYSCLK_CPU_BUS), 2));
267 clk_dm(JH7110_SYSCLK_PERH_ROOT,
268 starfive_clk_composite(priv->reg,
269 "perh_root",
270 perh_root_sels, ARRAY_SIZE(perh_root_sels),
271 OFFSET(JH7110_SYSCLK_PERH_ROOT), 1, 0, 2));
272 clk_dm(JH7110_SYSCLK_BUS_ROOT,
273 starfive_clk_mux(priv->reg, "bus_root",
274 OFFSET(JH7110_SYSCLK_BUS_ROOT), 1,
275 bus_root_sels, ARRAY_SIZE(bus_root_sels)));
276 clk_dm(JH7110_SYSCLK_NOCSTG_BUS,
277 starfive_clk_divider(priv->reg,
278 "nocstg_bus", "bus_root",
279 OFFSET(JH7110_SYSCLK_NOCSTG_BUS), 3));
280 clk_dm(JH7110_SYSCLK_AXI_CFG0,
281 starfive_clk_divider(priv->reg,
282 "axi_cfg0", "bus_root",
283 OFFSET(JH7110_SYSCLK_AXI_CFG0), 2));
284 clk_dm(JH7110_SYSCLK_STG_AXIAHB,
285 starfive_clk_divider(priv->reg,
286 "stg_axiahb", "axi_cfg0",
287 OFFSET(JH7110_SYSCLK_STG_AXIAHB), 2));
288 clk_dm(JH7110_SYSCLK_AHB0,
289 starfive_clk_gate(priv->reg,
290 "ahb0", "stg_axiahb",
291 OFFSET(JH7110_SYSCLK_AHB0)));
292 clk_dm(JH7110_SYSCLK_AHB1,
293 starfive_clk_gate(priv->reg,
294 "ahb1", "stg_axiahb",
295 OFFSET(JH7110_SYSCLK_AHB1)));
296 clk_dm(JH7110_SYSCLK_APB_BUS,
297 starfive_clk_divider(priv->reg,
298 "apb_bus", "stg_axiahb",
299 OFFSET(JH7110_SYSCLK_APB_BUS), 4));
300 clk_dm(JH7110_SYSCLK_APB0,
301 starfive_clk_gate(priv->reg,
302 "apb0", "apb_bus",
303 OFFSET(JH7110_SYSCLK_APB0)));
304 clk_dm(JH7110_SYSCLK_QSPI_AHB,
305 starfive_clk_gate(priv->reg,
306 "qspi_ahb", "ahb1",
307 OFFSET(JH7110_SYSCLK_QSPI_AHB)));
308 clk_dm(JH7110_SYSCLK_QSPI_APB,
309 starfive_clk_gate(priv->reg,
310 "qspi_apb", "apb_bus",
311 OFFSET(JH7110_SYSCLK_QSPI_APB)));
312 clk_dm(JH7110_SYSCLK_QSPI_REF_SRC,
313 starfive_clk_divider(priv->reg,
314 "qspi_ref_src", "pll0_out",
315 OFFSET(JH7110_SYSCLK_QSPI_REF_SRC), 5));
316 clk_dm(JH7110_SYSCLK_QSPI_REF,
317 starfive_clk_composite(priv->reg,
318 "qspi_ref",
319 qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
320 OFFSET(JH7110_SYSCLK_QSPI_REF), 1, 1, 0));
321 clk_dm(JH7110_SYSCLK_SDIO0_AHB,
322 starfive_clk_gate(priv->reg,
323 "sdio0_ahb", "ahb0",
324 OFFSET(JH7110_SYSCLK_SDIO0_AHB)));
325 clk_dm(JH7110_SYSCLK_SDIO1_AHB,
326 starfive_clk_gate(priv->reg,
327 "sdio1_ahb", "ahb0",
328 OFFSET(JH7110_SYSCLK_SDIO1_AHB)));
329 clk_dm(JH7110_SYSCLK_SDIO0_SDCARD,
330 starfive_clk_fix_parent_composite(priv->reg,
331 "sdio0_sdcard", "axi_cfg0",
332 OFFSET(JH7110_SYSCLK_SDIO0_SDCARD), 0, 1, 4));
333 clk_dm(JH7110_SYSCLK_SDIO1_SDCARD,
334 starfive_clk_fix_parent_composite(priv->reg,
335 "sdio1_sdcard", "axi_cfg0",
336 OFFSET(JH7110_SYSCLK_SDIO1_SDCARD), 0, 1, 4));
337 clk_dm(JH7110_SYSCLK_USB_125M,
338 starfive_clk_divider(priv->reg,
339 "usb_125m", "pll0_out",
340 OFFSET(JH7110_SYSCLK_USB_125M), 4));
341 clk_dm(JH7110_SYSCLK_NOC_BUS_STG_AXI,
342 starfive_clk_gate(priv->reg,
343 "noc_bus_stg_axi", "nocstg_bus",
344 OFFSET(JH7110_SYSCLK_NOC_BUS_STG_AXI)));
345 clk_dm(JH7110_SYSCLK_GMAC1_AHB,
346 starfive_clk_gate(priv->reg,
347 "gmac1_ahb", "ahb0",
348 OFFSET(JH7110_SYSCLK_GMAC1_AHB)));
349 clk_dm(JH7110_SYSCLK_GMAC1_AXI,
350 starfive_clk_gate(priv->reg,
351 "gmac1_axi", "stg_axiahb",
352 OFFSET(JH7110_SYSCLK_GMAC1_AXI)));
353 clk_dm(JH7110_SYSCLK_GMAC_SRC,
354 starfive_clk_divider(priv->reg,
355 "gmac_src", "pll0_out",
356 OFFSET(JH7110_SYSCLK_GMAC_SRC), 3));
357 clk_dm(JH7110_SYSCLK_GMAC1_GTXCLK,
358 starfive_clk_divider(priv->reg,
359 "gmac1_gtxclk", "pll0_out",
360 OFFSET(JH7110_SYSCLK_GMAC1_GTXCLK), 4));
361 clk_dm(JH7110_SYSCLK_GMAC1_GTXC,
362 starfive_clk_gate(priv->reg,
363 "gmac1_gtxc", "gmac1_gtxclk",
364 OFFSET(JH7110_SYSCLK_GMAC1_GTXC)));
365 clk_dm(JH7110_SYSCLK_GMAC1_RMII_RTX,
366 starfive_clk_divider(priv->reg,
367 "gmac1_rmii_rtx", "gmac1-rmii-refin-clock",
368 OFFSET(JH7110_SYSCLK_GMAC1_RMII_RTX), 5));
369 clk_dm(JH7110_SYSCLK_GMAC1_PTP,
370 starfive_clk_gate_divider(priv->reg,
371 "gmac1_ptp", "gmac_src",
372 OFFSET(JH7110_SYSCLK_GMAC1_PTP), 5));
373 clk_dm(JH7110_SYSCLK_GMAC1_RX,
374 starfive_clk_mux(priv->reg, "gmac1_rx",
375 OFFSET(JH7110_SYSCLK_GMAC1_RX), 1,
376 gmac1_rx_sels, ARRAY_SIZE(gmac1_rx_sels)));
377 clk_dm(JH7110_SYSCLK_GMAC1_TX,
378 starfive_clk_composite(priv->reg,
379 "gmac1_tx",
380 gmac1_tx_sels, ARRAY_SIZE(gmac1_tx_sels),
381 OFFSET(JH7110_SYSCLK_GMAC1_TX), 1, 1, 0));
382 clk_dm(JH7110_SYSCLK_GMAC1_TX_INV,
383 starfive_clk_inv(priv->reg,
384 "gmac1_tx_inv", "gmac1_tx",
385 OFFSET(JH7110_SYSCLK_GMAC1_TX_INV)));
386 clk_dm(JH7110_SYSCLK_GMAC0_GTXCLK,
387 starfive_clk_gate_divider(priv->reg,
388 "gmac0_gtxclk", "pll0_out",
389 OFFSET(JH7110_SYSCLK_GMAC0_GTXCLK), 4));
390 clk_dm(JH7110_SYSCLK_GMAC0_PTP,
391 starfive_clk_gate_divider(priv->reg,
392 "gmac0_ptp", "gmac_src",
393 OFFSET(JH7110_SYSCLK_GMAC0_PTP), 5));
394 clk_dm(JH7110_SYSCLK_GMAC0_GTXC,
395 starfive_clk_gate(priv->reg,
396 "gmac0_gtxc", "gmac0_gtxclk",
397 OFFSET(JH7110_SYSCLK_GMAC0_GTXC)));
398 clk_dm(JH7110_SYSCLK_UART0_APB,
399 starfive_clk_gate(priv->reg,
400 "uart0_apb", "apb0",
401 OFFSET(JH7110_SYSCLK_UART0_APB)));
402 clk_dm(JH7110_SYSCLK_UART0_CORE,
403 starfive_clk_gate(priv->reg,
404 "uart0_core", "oscillator",
405 OFFSET(JH7110_SYSCLK_UART0_CORE)));
406 clk_dm(JH7110_SYSCLK_UART1_APB,
407 starfive_clk_gate(priv->reg,
408 "uart1_apb", "apb0",
409 OFFSET(JH7110_SYSCLK_UART1_APB)));
410 clk_dm(JH7110_SYSCLK_UART1_CORE,
411 starfive_clk_gate(priv->reg,
412 "uart1_core", "oscillator",
413 OFFSET(JH7110_SYSCLK_UART1_CORE)));
414 clk_dm(JH7110_SYSCLK_UART2_APB,
415 starfive_clk_gate(priv->reg,
416 "uart2_apb", "apb0",
417 OFFSET(JH7110_SYSCLK_UART2_APB)));
418 clk_dm(JH7110_SYSCLK_UART2_CORE,
419 starfive_clk_gate(priv->reg,
420 "uart2_core", "oscillator",
421 OFFSET(JH7110_SYSCLK_UART2_CORE)));
422 clk_dm(JH7110_SYSCLK_UART3_APB,
423 starfive_clk_gate(priv->reg,
424 "uart3_apb", "apb0",
425 OFFSET(JH7110_SYSCLK_UART3_APB)));
426 clk_dm(JH7110_SYSCLK_UART3_CORE,
427 starfive_clk_gate_divider(priv->reg,
428 "uart3_core", "perh_root",
429 OFFSET(JH7110_SYSCLK_UART3_CORE), 8));
430 clk_dm(JH7110_SYSCLK_UART4_APB,
431 starfive_clk_gate(priv->reg,
432 "uart4_apb", "apb0",
433 OFFSET(JH7110_SYSCLK_UART4_APB)));
434 clk_dm(JH7110_SYSCLK_UART4_CORE,
435 starfive_clk_gate_divider(priv->reg,
436 "uart4_core", "perh_root",
437 OFFSET(JH7110_SYSCLK_UART4_CORE), 8));
438 clk_dm(JH7110_SYSCLK_UART5_APB,
439 starfive_clk_gate(priv->reg,
440 "uart5_apb", "apb0",
441 OFFSET(JH7110_SYSCLK_UART5_APB)));
442 clk_dm(JH7110_SYSCLK_UART5_CORE,
443 starfive_clk_gate_divider(priv->reg,
444 "uart5_core", "perh_root",
445 OFFSET(JH7110_SYSCLK_UART5_CORE), 8));
446 clk_dm(JH7110_SYSCLK_I2C2_APB,
447 starfive_clk_gate(priv->reg,
448 "i2c2_apb", "apb0",
449 OFFSET(JH7110_SYSCLK_I2C2_APB)));
450 clk_dm(JH7110_SYSCLK_I2C5_APB,
451 starfive_clk_gate(priv->reg,
452 "i2c5_apb", "apb0",
453 OFFSET(JH7110_SYSCLK_I2C5_APB)));
454
455 /* enable noc_bus_stg_axi clock */
456 if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))
457 clk_enable(pclk);
458
459 return 0;
460}
461
462static int jh7110_aoncrg_init(struct udevice *dev)
463{
464 struct jh7110_clk_priv *priv = dev_get_priv(dev);
465
466 clk_dm(JH7110_AONCLK_OSC_DIV4,
467 starfive_clk_divider(priv->reg,
468 "osc_div4", "oscillator",
469 AONOFFSET(JH7110_AONCLK_OSC_DIV4), 5));
470 clk_dm(JH7110_AONCLK_APB_FUNC,
471 starfive_clk_mux(priv->reg, "apb_func",
472 AONOFFSET(JH7110_AONCLK_APB_FUNC), 1,
473 apb_func_sels, ARRAY_SIZE(apb_func_sels)));
474 clk_dm(JH7110_AONCLK_GMAC0_AHB,
475 starfive_clk_gate(priv->reg,
476 "gmac0_ahb", "stg_axiahb",
477 AONOFFSET(JH7110_AONCLK_GMAC0_AHB)));
478 clk_dm(JH7110_AONCLK_GMAC0_AXI,
479 starfive_clk_gate(priv->reg,
480 "gmac0_axi", "stg_axiahb",
481 AONOFFSET(JH7110_AONCLK_GMAC0_AXI)));
482 clk_dm(JH7110_AONCLK_GMAC0_RMII_RTX,
483 starfive_clk_divider(priv->reg,
484 "gmac0_rmii_rtx", "gmac0-rmii-refin-clock",
485 AONOFFSET(JH7110_AONCLK_GMAC0_RMII_RTX), 5));
486 clk_dm(JH7110_AONCLK_GMAC0_TX,
487 starfive_clk_composite(priv->reg,
488 "gmac0_tx", gmac0_tx_sels,
489 ARRAY_SIZE(gmac0_tx_sels),
490 AONOFFSET(JH7110_AONCLK_GMAC0_TX), 1, 1, 0));
491 clk_dm(JH7110_AONCLK_GMAC0_TX_INV,
492 starfive_clk_inv(priv->reg,
493 "gmac0_tx_inv", "gmac0_tx",
494 AONOFFSET(JH7110_AONCLK_GMAC0_TX_INV)));
495 clk_dm(JH7110_AONCLK_OTPC_APB,
496 starfive_clk_gate(priv->reg,
497 "otpc_apb", "apb_bus",
498 AONOFFSET(JH7110_AONCLK_OTPC_APB)));
499
500 return 0;
501}
502
503static int jh7110_stgcrg_init(struct udevice *dev)
504{
505 struct jh7110_clk_priv *priv = dev_get_priv(dev);
506
507 clk_dm(JH7110_STGCLK_USB_APB,
508 starfive_clk_gate(priv->reg,
509 "usb_apb", "apb_bus",
510 STGOFFSET(JH7110_STGCLK_USB_APB)));
511 clk_dm(JH7110_STGCLK_USB_UTMI_APB,
512 starfive_clk_gate(priv->reg,
513 "usb_utmi_apb", "apb_bus",
514 STGOFFSET(JH7110_STGCLK_USB_UTMI_APB)));
515 clk_dm(JH7110_STGCLK_USB_AXI,
516 starfive_clk_gate(priv->reg,
517 "usb_axi", "stg_axiahb",
518 STGOFFSET(JH7110_STGCLK_USB_AXI)));
519 clk_dm(JH7110_STGCLK_USB_LPM,
520 starfive_clk_gate_divider(priv->reg,
521 "usb_lpm", "oscillator",
522 STGOFFSET(JH7110_STGCLK_USB_LPM), 2));
523 clk_dm(JH7110_STGCLK_USB_STB,
524 starfive_clk_gate_divider(priv->reg,
525 "usb_stb", "oscillator",
526 STGOFFSET(JH7110_STGCLK_USB_STB), 3));
527 clk_dm(JH7110_STGCLK_USB_APP_125,
528 starfive_clk_gate(priv->reg,
529 "usb_app_125", "usb_125m",
530 STGOFFSET(JH7110_STGCLK_USB_APP_125)));
531 clk_dm(JH7110_STGCLK_USB_REFCLK,
532 starfive_clk_divider(priv->reg, "usb_refclk", "oscillator",
533 STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2));
534 clk_dm(JH7110_STGCLK_PCIE0_AXI,
535 starfive_clk_gate(priv->reg,
536 "pcie0_axi", "stg_axiahb",
537 STGOFFSET(JH7110_STGCLK_PCIE0_AXI)));
538 clk_dm(JH7110_STGCLK_PCIE0_APB,
539 starfive_clk_gate(priv->reg,
540 "pcie0_apb", "apb_bus",
541 STGOFFSET(JH7110_STGCLK_PCIE0_APB)));
542 clk_dm(JH7110_STGCLK_PCIE0_TL,
543 starfive_clk_gate(priv->reg,
544 "pcie0_tl", "stg_axiahb",
545 STGOFFSET(JH7110_STGCLK_PCIE0_TL)));
546 clk_dm(JH7110_STGCLK_PCIE1_AXI,
547 starfive_clk_gate(priv->reg,
548 "pcie1_axi", "stg_axiahb",
549 STGOFFSET(JH7110_STGCLK_PCIE1_AXI)));
550 clk_dm(JH7110_STGCLK_PCIE1_APB,
551 starfive_clk_gate(priv->reg,
552 "pcie1_apb", "apb_bus",
553 STGOFFSET(JH7110_STGCLK_PCIE1_APB)));
554 clk_dm(JH7110_STGCLK_PCIE1_TL,
555 starfive_clk_gate(priv->reg,
556 "pcie1_tl", "stg_axiahb",
557 STGOFFSET(JH7110_STGCLK_PCIE1_TL)));
558
559 return 0;
560}
561
562static int jh7110_clk_probe(struct udevice *dev)
563{
564 struct jh7110_clk_priv *priv = dev_get_priv(dev);
565
566 priv->init = (jh1710_init_fn)dev_get_driver_data(dev);
567 priv->reg = (void __iomem *)dev_read_addr_ptr(dev);
568
569 if (priv->init)
570 return priv->init(dev);
571
572 return 0;
573}
574
575static int jh7110_clk_bind(struct udevice *dev)
576{
577 /* The reset driver does not have a device node, so bind it here */
578 return device_bind_driver_to_node(dev, "jh7110_reset", dev->name,
579 dev_ofnode(dev), NULL);
580}
581
582static const struct udevice_id jh7110_clk_of_match[] = {
583 { .compatible = "starfive,jh7110-syscrg",
584 .data = (ulong)&jh7110_syscrg_init
585 },
586 { .compatible = "starfive,jh7110-stgcrg",
587 .data = (ulong)&jh7110_stgcrg_init
588 },
589 { .compatible = "starfive,jh7110-aoncrg",
590 .data = (ulong)&jh7110_aoncrg_init
591 },
592 { }
593};
594
595U_BOOT_DRIVER(jh7110_clk) = {
596 .name = "jh7110_clk",
597 .id = UCLASS_CLK,
598 .of_match = jh7110_clk_of_match,
599 .probe = jh7110_clk_probe,
600 .ops = &ccf_clk_ops,
601 .priv_auto = sizeof(struct jh7110_clk_priv),
602 .bind = jh7110_clk_bind,
603};