Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 5a6b52b929a916443c4c80fe8b18d224420dae71 / . / configs / ls1012aqds_qspi_defconfig
blob: d2c3eea43bb7a4e4e82a80ea8f045e5c3ef2eea1 [file] [log] [blame]
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]1CONFIG_ARM=y
2CONFIG_TARGET_LS1012AQDS=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x40100000
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]4CONFIG_FSL_LS_PPA=y
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]5CONFIG_QSPI_AHB_INIT=y
Tom Rinid9669f12018-08-07 21:40:14 -0400[diff] [blame]6CONFIG_AHCI=y
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]7CONFIG_DISTRO_DEFAULTS=y
Tom Rinif2260382018-08-16 08:16:24 -0400[diff] [blame]8CONFIG_NR_DRAM_BANKS=2
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]9# CONFIG_SYS_MALLOC_F is not set
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]10CONFIG_FIT_VERBOSE=y
11CONFIG_OF_BOARD_SETUP=y
12CONFIG_OF_STDOUT_VIA_ALIAS=y
13CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
Tom Rini0d130ad2016-06-27 22:40:17 -0400[diff] [blame]14CONFIG_QSPI_BOOT=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]15CONFIG_BOOTDELAY=10
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]16CONFIG_USE_BOOTARGS=y
17CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]18# CONFIG_USE_BOOTCOMMAND is not set
Adam Ford10541762018-07-29 13:13:29 -0500[diff] [blame]19CONFIG_MISC_INIT_R=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]20# CONFIG_DISPLAY_BOARDINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]21CONFIG_DISPLAY_BOARDINFO_LATE=y
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]22CONFIG_CMD_GREPENV=y
Simon Glass4590d4e2017-05-17 03:25:10 -0600[diff] [blame]23CONFIG_CMD_EEPROM=y
Mario Six00518992018-03-28 14:38:14 +0200[diff] [blame]24CONFIG_CMD_MEMTEST=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]25CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]26CONFIG_CMD_I2C=y
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]27CONFIG_CMD_MMC=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]28CONFIG_CMD_PCI=y
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]29CONFIG_CMD_SF=y
Patrick Delaunay5a6b52b2019-02-27 15:20:37 +0100[diff] [blame^]30CONFIG_CMD_SPI=y
31CONFIG_DEFAULT_SPI_BUS=1
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]32CONFIG_CMD_USB=y
Patrick Delaunay5a6b52b2019-02-27 15:20:37 +0100[diff] [blame^]33CONFIG_DEFAULT_SPI_BUS=1
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]34# CONFIG_CMD_SETEXPR is not set
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]35CONFIG_CMD_CACHE=y
Chris Packham3e257df2017-04-29 15:20:28 +1200[diff] [blame]36CONFIG_CMD_DATE=y
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]37CONFIG_OF_CONTROL=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]38CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]39CONFIG_ENV_IS_IN_SPI_FLASH=y
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]40CONFIG_NET_RANDOM_ETHADDR=y
41CONFIG_DM=y
Tuomas Tynkkynenedf9f622017-12-08 15:36:19 +0200[diff] [blame]42CONFIG_SCSI_AHCI=y
Tom Rinid9669f12018-08-07 21:40:14 -0400[diff] [blame]43CONFIG_SATA_CEVA=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]44CONFIG_DM_MMC=y
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]45CONFIG_FSL_ESDHC=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]46CONFIG_DM_SPI_FLASH=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]47CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]48CONFIG_SF_DEFAULT_BUS=1
49CONFIG_SF_DEFAULT_MODE=0
50CONFIG_SF_DEFAULT_SPEED=10000000
Ashish Kumar3c2065d2018-06-26 14:48:30 +0530[diff] [blame]51# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
Tom Rini9bd09622018-04-07 20:27:54 -0400[diff] [blame]52CONFIG_FSL_PFE=y
Calvin Johnson0e6101a2018-03-08 15:30:35 +0530[diff] [blame]53CONFIG_DM_ETH=y
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]54CONFIG_E1000=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]55CONFIG_PCI=y
56CONFIG_DM_PCI=y
57CONFIG_DM_PCI_COMPAT=y
58CONFIG_PCIE_LAYERSCAPE=y
Tom Rinie791a022017-08-11 11:20:19 -0400[diff] [blame]59CONFIG_SCSI=y
Tom Rinid9669f12018-08-07 21:40:14 -0400[diff] [blame]60CONFIG_DM_SCSI=y
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]61CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]62CONFIG_SPI=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]63CONFIG_DM_SPI=y
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]64CONFIG_FSL_DSPI=y
Tom Rinifaffdfd2016-06-06 10:04:58 -0400[diff] [blame]65CONFIG_USB=y
Tang Yuantian67df7de2016-12-27 10:24:45 +0800[diff] [blame]66CONFIG_DM_USB=y
Tom Rinifaffdfd2016-06-06 10:04:58 -0400[diff] [blame]67CONFIG_USB_XHCI_HCD=y
68CONFIG_USB_XHCI_DWC3=y