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git01.mediatek.com / filogic / uboot / 5a15c1a67f65f494eb57324f00ae28ad91caf5b5 / . / arch / arm / dts / tegra20-colibri.dts
blob: 2cf24d3ee7711031196609608a449afafb077d37 [file] [log] [blame]
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]4
5/ {
6 model = "Toradex Colibri T20";
Marcel Ziswiler2ec89a82015-08-06 00:47:01 +0200[diff] [blame]7 compatible = "toradex,colibri_t20", "nvidia,tegra20";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]13 aliases {
Marcel Ziswiler9a520202015-08-06 00:47:03 +0200[diff] [blame]14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]17 usb0 = "/usb@c5008000";
18 usb1 = "/usb@c5000000";
19 usb2 = "/usb@c5004000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]20 sdhci0 = "/sdhci@c8000600";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]21 };
22
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]23 host1x@50000000 {
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]24 status = "okay";
25 dc@54200000 {
26 status = "okay";
27 rgb {
28 status = "okay";
29 nvidia,panel = <&lcd_panel>;
30 };
31 };
32 };
33
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]34 usb@c5000000 {
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]35 statuc = "okay";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]36 dr_mode = "otg";
37 };
38
39 usb@c5004000 {
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]40 statuc = "okay";
Marcel Ziswiler764d4122015-08-06 00:47:10 +0200[diff] [blame]41 /* VBUS_LAN */
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]42 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
43 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]44 };
45
46 usb@c5008000 {
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]47 statuc = "okay";
Marcel Ziswiler764d4122015-08-06 00:47:10 +0200[diff] [blame]48 /* USBH_PEN */
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]49 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]50 };
51
52 nand-controller@70008000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]53 nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]54 nvidia,width = <8>;
55 nvidia,timing = <15 100 25 80 25 10 15 10 100>;
56
57 nand@0 {
58 reg = <0>;
59 compatible = "nand-flash";
60 };
61 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]62
Marcel Ziswiler9a520202015-08-06 00:47:03 +0200[diff] [blame]63 /*
64 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
65 * board)
66 */
67 i2c@7000c000 {
68 status = "okay";
69 clock-frequency = <100000>;
70 };
71
72 /* GEN2_I2C: unused */
73
74 /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
75 i2c@7000c400 {
76 status = "okay";
77 clock-frequency = <100000>;
78 };
79
80 /*
81 * PWR_I2C: power I2C to PMIC and temperature sensor
82 */
83 i2c@7000d000 {
84 status = "okay";
85 clock-frequency = <100000>;
86 };
87
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]88 sdhci@c8000600 {
89 status = "okay";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]90 bus-width = <4>;
Marcel Ziswiler764d4122015-08-06 00:47:10 +0200[diff] [blame]91 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]92 };
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]93
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]94 clocks {
95 compatible = "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 clk32k_in: clock@0 {
100 compatible = "fixed-clock";
101 reg=<0>;
102 #clock-cells = <0>;
103 clock-frequency = <32768>;
104 };
105 };
106
Simon Glassd8af3c92016-01-30 16:38:01 -0700[diff] [blame]107 pwm: pwm@7000a000 {
108 status = "okay";
109 };
110
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]111 lcd_panel: panel {
112 clock = <25175000>;
113 xres = <640>;
114 yres = <480>;
115 left-margin = <48>; /* horizontal back porch */
116 right-margin = <16>; /* horizontal front porch */
117 hsync-len = <96>;
118 lower-margin = <11>; /* vertical front porch */
119 upper-margin = <31>; /* vertical back porch */
120 vsync-len = <2>;
121 hsync-active-high;
122 vsync-active-high;
123 nvidia,bits-per-pixel = <16>;
124 nvidia,pwm = <&pwm 0 0>;
125 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
126 nvidia,panel-timings = <0 0 0 0>;
127 };
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]128};