Mario Six | 53fbdd1 | 2019-03-29 10:18:17 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Basic platform for gdsys mpc8308 based devices |
| 3 | * |
| 4 | * (C) Copyright 2014 |
| 5 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
| 6 | * |
| 7 | * based on mpc8308rdb |
| 8 | * Copyright 2009 Freescale Semiconductor Inc. |
| 9 | * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the |
| 13 | * Free Software Foundation; either version 2 of the License, or (at your |
| 14 | * option) any later version. |
| 15 | */ |
| 16 | |
| 17 | /dts-v1/; |
| 18 | |
| 19 | #include <dt-bindings/memory/mpc83xx-sdram.h> |
Rasmus Villemoes | 595793b | 2020-02-11 15:20:23 +0000 | [diff] [blame^] | 20 | #include <dt-bindings/clk/mpc83xx-clk.h> |
Mario Six | 53fbdd1 | 2019-03-29 10:18:17 +0100 | [diff] [blame] | 21 | |
| 22 | / { |
| 23 | compatible = "fsl,mpc8308rdb"; |
| 24 | |
| 25 | #address-cells = <1>; |
| 26 | #size-cells = <1>; |
| 27 | |
| 28 | aliases { |
| 29 | serial0 = &serial0; |
| 30 | serial1 = &serial1; |
| 31 | }; |
| 32 | |
| 33 | memory { |
| 34 | device_type = "memory"; |
| 35 | }; |
| 36 | |
| 37 | cpus { |
| 38 | #address-cells = <1>; |
| 39 | #size-cells = <0>; |
| 40 | |
| 41 | PowerPC,8308@0 { |
| 42 | device_type = "cpu"; |
| 43 | reg = <0x0>; |
| 44 | d-cache-line-size = <32>; |
| 45 | i-cache-line-size = <32>; |
| 46 | d-cache-size = <16384>; |
| 47 | i-cache-size = <16384>; |
| 48 | timebase-frequency = <0>; // from bootloader |
| 49 | bus-frequency = <0>; // from bootloader |
| 50 | clock-frequency = <0>; // from bootloader |
| 51 | }; |
| 52 | }; |
| 53 | |
Rasmus Villemoes | 595793b | 2020-02-11 15:20:23 +0000 | [diff] [blame^] | 54 | socclocks: clocks { |
| 55 | compatible = "fsl,mpc8308-clk"; |
| 56 | #clock-cells = <1>; |
| 57 | }; |
| 58 | |
Mario Six | 53fbdd1 | 2019-03-29 10:18:17 +0100 | [diff] [blame] | 59 | board_lbc: localbus@e0005000 { |
| 60 | #address-cells = <2>; |
| 61 | #size-cells = <1>; |
| 62 | compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; |
| 63 | reg = <0xe0005000 0x1000>; |
| 64 | interrupts = <77 0x8>; |
| 65 | interrupt-parent = <&ipic>; |
| 66 | }; |
| 67 | |
| 68 | board_soc: immr@e0000000 { |
| 69 | #address-cells = <1>; |
| 70 | #size-cells = <1>; |
| 71 | device_type = "soc"; |
| 72 | compatible = "fsl,mpc8308-immr", "simple-bus"; |
| 73 | ranges = <0 0xe0000000 0x00100000>; |
| 74 | reg = <0xe0000000 0x00000200>; |
| 75 | bus-frequency = <0>; |
| 76 | |
| 77 | wdt@200 { |
| 78 | device_type = "watchdog"; |
| 79 | compatible = "mpc83xx_wdt"; |
| 80 | reg = <0x200 0x100>; |
| 81 | }; |
| 82 | |
| 83 | memory@2000 { |
| 84 | #address-cells = <2>; |
| 85 | #size-cells = <1>; |
| 86 | compatible = "fsl,mpc83xx-mem-controller"; |
| 87 | reg = <0x2000 0x1000>; |
| 88 | device_type = "memory"; |
| 89 | |
| 90 | driver_software_override = <DSO_ENABLE>; |
| 91 | p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>; |
| 92 | n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>; |
| 93 | odt_termination_value = <ODT_TERMINATION_150_OHM>; |
| 94 | ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>; |
| 95 | |
| 96 | clock_adjust = <CLOCK_ADJUST_05>; |
| 97 | |
| 98 | read_to_write = <0>; |
| 99 | write_to_read = <0>; |
| 100 | read_to_read = <0>; |
| 101 | write_to_write = <0>; |
| 102 | active_powerdown_exit = <2>; |
| 103 | precharge_powerdown_exit = <6>; |
| 104 | odt_powerdown_exit = <8>; |
| 105 | mode_reg_set_cycle = <2>; |
| 106 | |
| 107 | precharge_to_activate = <2>; |
| 108 | activate_to_precharge = <6>; |
| 109 | activate_to_readwrite = <2>; |
| 110 | mcas_latency = <CASLAT_40>; |
| 111 | refresh_recovery = <17>; |
| 112 | last_data_to_precharge = <2>; |
| 113 | activate_to_activate = <2>; |
| 114 | last_write_data_to_read = <2>; |
| 115 | |
| 116 | additive_latency = <0>; |
| 117 | mcas_to_preamble_override = <READ_LAT_PLUS_1_2>; |
| 118 | write_latency = <3>; |
| 119 | read_to_precharge = <2>; |
| 120 | write_cmd_to_write_data = <CLOCK_DELAY_1_2>; |
| 121 | minimum_cke_pulse_width = <3>; |
| 122 | four_activates_window = <5>; |
| 123 | |
| 124 | self_refresh = <SREN_ENABLE>; |
| 125 | sdram_type = <TYPE_DDR2>; |
| 126 | databus_width = <DATA_BUS_WIDTH_32>; |
| 127 | |
| 128 | force_self_refresh = <MODE_NORMAL>; |
| 129 | dll_reset = <DLL_RESET_ENABLE>; |
| 130 | dqs_config = <DQS_TRUE>; |
| 131 | odt_config = <ODT_ASSERT_READS>; |
| 132 | posted_refreshes = <1>; |
| 133 | |
| 134 | refresh_interval = <2084>; |
| 135 | precharge_interval = <256>; |
| 136 | |
| 137 | sdmode = <0x0242>; |
| 138 | esdmode = <0x0440>; |
| 139 | |
| 140 | ram@0 { |
| 141 | reg = <0x0 0x0 0x8000000>; |
| 142 | compatible = "nanya,nt5tu64m16hg"; |
| 143 | |
| 144 | odt_rd_cfg = <ODT_RD_NEVER>; |
| 145 | odt_wr_cfg = <ODT_WR_ONLY_CURRENT>; |
| 146 | bank_bits = <3>; |
| 147 | row_bits = <13>; |
| 148 | col_bits = <10>; |
| 149 | }; |
| 150 | }; |
| 151 | |
| 152 | IIC:i2c@3000 { |
| 153 | #address-cells = <1>; |
| 154 | #size-cells = <0>; |
| 155 | cell-index = <0>; |
| 156 | compatible = "fsl-i2c"; |
| 157 | reg = <0x3000 0x100>; |
| 158 | interrupts = <14 0x8>; |
| 159 | interrupt-parent = <&ipic>; |
| 160 | dfsrr; |
| 161 | }; |
| 162 | |
| 163 | IIC2: i2c@3100 { |
| 164 | #address-cells = <1>; |
| 165 | #size-cells = <0>; |
| 166 | compatible = "fsl-i2c"; |
| 167 | reg = <0x3100 0x100>; |
| 168 | interrupts = <15 0x8>; |
| 169 | interrupt-parent = <&ipic>; |
| 170 | dfsrr; |
| 171 | status = "disabled"; |
| 172 | }; |
| 173 | |
| 174 | SPI:spi@7000 { |
| 175 | #address-cells = <1>; |
| 176 | #size-cells = <0>; |
| 177 | cell-index = <0>; |
| 178 | compatible = "fsl,spi"; |
| 179 | reg = <0x7000 0x1000>; |
| 180 | interrupts = <16 0x8>; |
| 181 | interrupt-parent = <&ipic>; |
Rasmus Villemoes | 595793b | 2020-02-11 15:20:23 +0000 | [diff] [blame^] | 182 | clocks = <&socclocks MPC83XX_CLK_CSB>; |
Mario Six | 53fbdd1 | 2019-03-29 10:18:17 +0100 | [diff] [blame] | 183 | mode = "cpu"; |
| 184 | }; |
| 185 | |
| 186 | sdhc@2e000 { |
| 187 | compatible = "fsl,esdhc", "fsl,mpc8308-esdhc"; |
| 188 | reg = <0x2e000 0x1000>; |
| 189 | interrupts = <42 0x8>; |
| 190 | interrupt-parent = <&ipic>; |
| 191 | sdhci,auto-cmd12; |
| 192 | /* Filled in by U-Boot */ |
| 193 | clock-frequency = <0>; |
| 194 | }; |
| 195 | |
| 196 | serial0: serial@4500 { |
| 197 | cell-index = <0>; |
| 198 | device_type = "serial"; |
| 199 | compatible = "fsl,ns16550", "ns16550"; |
| 200 | reg = <0x4500 0x100>; |
| 201 | clock-frequency = <133333333>; |
| 202 | interrupts = <9 0x8>; |
| 203 | interrupt-parent = <&ipic>; |
| 204 | }; |
| 205 | |
| 206 | serial1: serial@4600 { |
| 207 | cell-index = <1>; |
| 208 | device_type = "serial"; |
| 209 | compatible = "fsl,ns16550", "ns16550"; |
| 210 | reg = <0x4600 0x100>; |
| 211 | clock-frequency = <133333333>; |
| 212 | interrupts = <10 0x8>; |
| 213 | interrupt-parent = <&ipic>; |
| 214 | }; |
| 215 | |
| 216 | gpio0: gpio@c00 { |
| 217 | #gpio-cells = <2>; |
| 218 | device_type = "gpio"; |
| 219 | compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio"; |
| 220 | reg = <0xc00 0x18>; |
| 221 | interrupts = <74 0x8>; |
| 222 | interrupt-parent = <&ipic>; |
| 223 | gpio-controller; |
| 224 | }; |
| 225 | |
| 226 | /* IPIC |
| 227 | * interrupts cell = <intr #, sense> |
| 228 | * sense values match linux IORESOURCE_IRQ_* defines: |
| 229 | * sense == 8: Level, low assertion |
| 230 | * sense == 2: Edge, high-to-low change |
| 231 | */ |
| 232 | ipic: interrupt-controller@700 { |
| 233 | compatible = "fsl,ipic"; |
| 234 | interrupt-controller; |
| 235 | #address-cells = <0>; |
| 236 | #interrupt-cells = <2>; |
| 237 | reg = <0x700 0x100>; |
| 238 | device_type = "ipic"; |
| 239 | }; |
| 240 | |
| 241 | ipic-msi@7c0 { |
| 242 | compatible = "fsl,ipic-msi"; |
| 243 | reg = <0x7c0 0x40>; |
| 244 | msi-available-ranges = <0x0 0x100>; |
| 245 | interrupts = < 0x43 0x8 |
| 246 | 0x4 0x8 |
| 247 | 0x51 0x8 |
| 248 | 0x52 0x8 |
| 249 | 0x56 0x8 |
| 250 | 0x57 0x8 |
| 251 | 0x58 0x8 |
| 252 | 0x59 0x8 >; |
| 253 | interrupt-parent = < &ipic >; |
| 254 | }; |
| 255 | |
| 256 | dma@2c000 { |
| 257 | compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma"; |
| 258 | reg = <0x2c000 0x1800>; |
| 259 | interrupts = <3 0x8 |
| 260 | 94 0x8>; |
| 261 | interrupt-parent = < &ipic >; |
| 262 | }; |
| 263 | |
| 264 | enet0: ethernet@24000 { |
| 265 | #address-cells = <1>; |
| 266 | #size-cells = <1>; |
| 267 | ranges = <0x0 0x24000 0x1000>; |
| 268 | |
| 269 | cell-index = <0>; |
| 270 | device_type = "network"; |
| 271 | model = "eTSEC"; |
| 272 | compatible = "gianfar", "fsl,tsec"; |
| 273 | reg = <0x24000 0x1000>; |
| 274 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 275 | interrupts = <32 0x8 33 0x8 34 0x8>; |
| 276 | interrupt-parent = <&ipic>; |
| 277 | tbi-handle = < &tbi0 >; |
| 278 | phy-handle = < &phy1 >; |
| 279 | fsl,magic-packet; |
| 280 | |
| 281 | mdio@520 { |
| 282 | #address-cells = <1>; |
| 283 | #size-cells = <0>; |
| 284 | compatible = "fsl,gianfar-mdio"; |
| 285 | reg = <0x520 0x20>; |
| 286 | phy1: ethernet-phy@1 { |
| 287 | reg = <0x1>; |
| 288 | }; |
| 289 | phy2: ethernet-phy@0 { |
| 290 | reg = <0x0>; |
| 291 | device_type = "ethernet-phy"; |
| 292 | }; |
| 293 | tbi0: tbi-phy@11 { |
| 294 | reg = <0x11>; |
| 295 | device_type = "tbi-phy"; |
| 296 | }; |
| 297 | }; |
| 298 | }; |
| 299 | |
| 300 | enet1: ethernet@25000 { |
| 301 | #address-cells = <1>; |
| 302 | #size-cells = <1>; |
| 303 | cell-index = <1>; |
| 304 | device_type = "network"; |
| 305 | model = "eTSEC"; |
| 306 | compatible = "gianfar", "fsl,tsec"; |
| 307 | reg = <0x25000 0x1000>; |
| 308 | ranges = <0x0 0x25000 0x1000>; |
| 309 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 310 | interrupts = <35 0x8 36 0x8 37 0x8>; |
| 311 | interrupt-parent = <&ipic>; |
| 312 | phy-handle = < &phy2 >; |
| 313 | status = "disabled"; |
| 314 | |
| 315 | mdio@520 { |
| 316 | #address-cells = <1>; |
| 317 | #size-cells = <0>; |
| 318 | compatible = "fsl,gianfar-tbi"; |
| 319 | reg = <0x520 0x20>; |
| 320 | tbi1: tbi-phy@11 { |
| 321 | reg = <0x11>; |
| 322 | device_type = "tbi-phy"; |
| 323 | }; |
| 324 | }; |
| 325 | }; |
| 326 | }; |
| 327 | |
| 328 | pci0: pcie@e0009000 { |
| 329 | #address-cells = <3>; |
| 330 | #size-cells = <2>; |
| 331 | #interrupt-cells = <1>; |
| 332 | device_type = "pci"; |
| 333 | compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie"; |
| 334 | reg = <0xe0009000 0x00001000 |
| 335 | 0xb0000000 0x01000000>; |
| 336 | ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 |
| 337 | 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; |
| 338 | bus-range = <0 0>; |
| 339 | interrupt-map-mask = <0xf800 0 0 7>; |
| 340 | interrupt-map = <0 0 0 1 &ipic 1 8 |
| 341 | 0 0 0 2 &ipic 1 8 |
| 342 | 0 0 0 3 &ipic 1 8 |
| 343 | 0 0 0 4 &ipic 1 8>; |
| 344 | interrupts = <0x1 0x8>; |
| 345 | interrupt-parent = <&ipic>; |
| 346 | clock-frequency = <0>; |
| 347 | |
| 348 | pcie@0 { |
| 349 | #address-cells = <3>; |
| 350 | #size-cells = <2>; |
| 351 | device_type = "pci"; |
| 352 | reg = <0 0 0 0 0>; |
| 353 | ranges = <0x02000000 0 0xa0000000 |
| 354 | 0x02000000 0 0xa0000000 |
| 355 | 0 0x10000000 |
| 356 | 0x01000000 0 0x00000000 |
| 357 | 0x01000000 0 0x00000000 |
| 358 | 0 0x00800000>; |
| 359 | }; |
| 360 | }; |
| 361 | }; |