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git01.mediatek.com / filogic / uboot / 53fbdd1a5ca8206ef582e4b80fb0f7cf854c0c9f / . / arch / powerpc / dts / gdsys / mpc8308.dtsi
blob: 23e7403d91102e392f8d917bd5ad7008ff6edcde [file] [log] [blame]
Mario Six53fbdd12019-03-29 10:18:17 +0100[diff] [blame^]1/*
2 * Basic platform for gdsys mpc8308 based devices
3 *
4 * (C) Copyright 2014
5 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 *
7 * based on mpc8308rdb
8 * Copyright 2009 Freescale Semiconductor Inc.
9 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17/dts-v1/;
18
19#include <dt-bindings/memory/mpc83xx-sdram.h>
20
21/ {
22 compatible = "fsl,mpc8308rdb";
23
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 aliases {
28 serial0 = &serial0;
29 serial1 = &serial1;
30 };
31
32 memory {
33 device_type = "memory";
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 PowerPC,8308@0 {
41 device_type = "cpu";
42 reg = <0x0>;
43 d-cache-line-size = <32>;
44 i-cache-line-size = <32>;
45 d-cache-size = <16384>;
46 i-cache-size = <16384>;
47 timebase-frequency = <0>; // from bootloader
48 bus-frequency = <0>; // from bootloader
49 clock-frequency = <0>; // from bootloader
50 };
51 };
52
53 board_lbc: localbus@e0005000 {
54 #address-cells = <2>;
55 #size-cells = <1>;
56 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
57 reg = <0xe0005000 0x1000>;
58 interrupts = <77 0x8>;
59 interrupt-parent = <&ipic>;
60 };
61
62 board_soc: immr@e0000000 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 device_type = "soc";
66 compatible = "fsl,mpc8308-immr", "simple-bus";
67 ranges = <0 0xe0000000 0x00100000>;
68 reg = <0xe0000000 0x00000200>;
69 bus-frequency = <0>;
70
71 wdt@200 {
72 device_type = "watchdog";
73 compatible = "mpc83xx_wdt";
74 reg = <0x200 0x100>;
75 };
76
77 memory@2000 {
78 #address-cells = <2>;
79 #size-cells = <1>;
80 compatible = "fsl,mpc83xx-mem-controller";
81 reg = <0x2000 0x1000>;
82 device_type = "memory";
83
84 driver_software_override = <DSO_ENABLE>;
85 p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
86 n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
87 odt_termination_value = <ODT_TERMINATION_150_OHM>;
88 ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
89
90 clock_adjust = <CLOCK_ADJUST_05>;
91
92 read_to_write = <0>;
93 write_to_read = <0>;
94 read_to_read = <0>;
95 write_to_write = <0>;
96 active_powerdown_exit = <2>;
97 precharge_powerdown_exit = <6>;
98 odt_powerdown_exit = <8>;
99 mode_reg_set_cycle = <2>;
100
101 precharge_to_activate = <2>;
102 activate_to_precharge = <6>;
103 activate_to_readwrite = <2>;
104 mcas_latency = <CASLAT_40>;
105 refresh_recovery = <17>;
106 last_data_to_precharge = <2>;
107 activate_to_activate = <2>;
108 last_write_data_to_read = <2>;
109
110 additive_latency = <0>;
111 mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
112 write_latency = <3>;
113 read_to_precharge = <2>;
114 write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
115 minimum_cke_pulse_width = <3>;
116 four_activates_window = <5>;
117
118 self_refresh = <SREN_ENABLE>;
119 sdram_type = <TYPE_DDR2>;
120 databus_width = <DATA_BUS_WIDTH_32>;
121
122 force_self_refresh = <MODE_NORMAL>;
123 dll_reset = <DLL_RESET_ENABLE>;
124 dqs_config = <DQS_TRUE>;
125 odt_config = <ODT_ASSERT_READS>;
126 posted_refreshes = <1>;
127
128 refresh_interval = <2084>;
129 precharge_interval = <256>;
130
131 sdmode = <0x0242>;
132 esdmode = <0x0440>;
133
134 ram@0 {
135 reg = <0x0 0x0 0x8000000>;
136 compatible = "nanya,nt5tu64m16hg";
137
138 odt_rd_cfg = <ODT_RD_NEVER>;
139 odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
140 bank_bits = <3>;
141 row_bits = <13>;
142 col_bits = <10>;
143 };
144 };
145
146 IIC:i2c@3000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 cell-index = <0>;
150 compatible = "fsl-i2c";
151 reg = <0x3000 0x100>;
152 interrupts = <14 0x8>;
153 interrupt-parent = <&ipic>;
154 dfsrr;
155 };
156
157 IIC2: i2c@3100 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl-i2c";
161 reg = <0x3100 0x100>;
162 interrupts = <15 0x8>;
163 interrupt-parent = <&ipic>;
164 dfsrr;
165 status = "disabled";
166 };
167
168 SPI:spi@7000 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 cell-index = <0>;
172 compatible = "fsl,spi";
173 reg = <0x7000 0x1000>;
174 interrupts = <16 0x8>;
175 interrupt-parent = <&ipic>;
176 mode = "cpu";
177 };
178
179 sdhc@2e000 {
180 compatible = "fsl,esdhc", "fsl,mpc8308-esdhc";
181 reg = <0x2e000 0x1000>;
182 interrupts = <42 0x8>;
183 interrupt-parent = <&ipic>;
184 sdhci,auto-cmd12;
185 /* Filled in by U-Boot */
186 clock-frequency = <0>;
187 };
188
189 serial0: serial@4500 {
190 cell-index = <0>;
191 device_type = "serial";
192 compatible = "fsl,ns16550", "ns16550";
193 reg = <0x4500 0x100>;
194 clock-frequency = <133333333>;
195 interrupts = <9 0x8>;
196 interrupt-parent = <&ipic>;
197 };
198
199 serial1: serial@4600 {
200 cell-index = <1>;
201 device_type = "serial";
202 compatible = "fsl,ns16550", "ns16550";
203 reg = <0x4600 0x100>;
204 clock-frequency = <133333333>;
205 interrupts = <10 0x8>;
206 interrupt-parent = <&ipic>;
207 };
208
209 gpio0: gpio@c00 {
210 #gpio-cells = <2>;
211 device_type = "gpio";
212 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
213 reg = <0xc00 0x18>;
214 interrupts = <74 0x8>;
215 interrupt-parent = <&ipic>;
216 gpio-controller;
217 };
218
219 /* IPIC
220 * interrupts cell = <intr #, sense>
221 * sense values match linux IORESOURCE_IRQ_* defines:
222 * sense == 8: Level, low assertion
223 * sense == 2: Edge, high-to-low change
224 */
225 ipic: interrupt-controller@700 {
226 compatible = "fsl,ipic";
227 interrupt-controller;
228 #address-cells = <0>;
229 #interrupt-cells = <2>;
230 reg = <0x700 0x100>;
231 device_type = "ipic";
232 };
233
234 ipic-msi@7c0 {
235 compatible = "fsl,ipic-msi";
236 reg = <0x7c0 0x40>;
237 msi-available-ranges = <0x0 0x100>;
238 interrupts = < 0x43 0x8
239 0x4 0x8
240 0x51 0x8
241 0x52 0x8
242 0x56 0x8
243 0x57 0x8
244 0x58 0x8
245 0x59 0x8 >;
246 interrupt-parent = < &ipic >;
247 };
248
249 dma@2c000 {
250 compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
251 reg = <0x2c000 0x1800>;
252 interrupts = <3 0x8
253 94 0x8>;
254 interrupt-parent = < &ipic >;
255 };
256
257 enet0: ethernet@24000 {
258 #address-cells = <1>;
259 #size-cells = <1>;
260 ranges = <0x0 0x24000 0x1000>;
261
262 cell-index = <0>;
263 device_type = "network";
264 model = "eTSEC";
265 compatible = "gianfar", "fsl,tsec";
266 reg = <0x24000 0x1000>;
267 local-mac-address = [ 00 00 00 00 00 00 ];
268 interrupts = <32 0x8 33 0x8 34 0x8>;
269 interrupt-parent = <&ipic>;
270 tbi-handle = < &tbi0 >;
271 phy-handle = < &phy1 >;
272 fsl,magic-packet;
273
274 mdio@520 {
275 #address-cells = <1>;
276 #size-cells = <0>;
277 compatible = "fsl,gianfar-mdio";
278 reg = <0x520 0x20>;
279 phy1: ethernet-phy@1 {
280 reg = <0x1>;
281 };
282 phy2: ethernet-phy@0 {
283 reg = <0x0>;
284 device_type = "ethernet-phy";
285 };
286 tbi0: tbi-phy@11 {
287 reg = <0x11>;
288 device_type = "tbi-phy";
289 };
290 };
291 };
292
293 enet1: ethernet@25000 {
294 #address-cells = <1>;
295 #size-cells = <1>;
296 cell-index = <1>;
297 device_type = "network";
298 model = "eTSEC";
299 compatible = "gianfar", "fsl,tsec";
300 reg = <0x25000 0x1000>;
301 ranges = <0x0 0x25000 0x1000>;
302 local-mac-address = [ 00 00 00 00 00 00 ];
303 interrupts = <35 0x8 36 0x8 37 0x8>;
304 interrupt-parent = <&ipic>;
305 phy-handle = < &phy2 >;
306 status = "disabled";
307
308 mdio@520 {
309 #address-cells = <1>;
310 #size-cells = <0>;
311 compatible = "fsl,gianfar-tbi";
312 reg = <0x520 0x20>;
313 tbi1: tbi-phy@11 {
314 reg = <0x11>;
315 device_type = "tbi-phy";
316 };
317 };
318 };
319 };
320
321 pci0: pcie@e0009000 {
322 #address-cells = <3>;
323 #size-cells = <2>;
324 #interrupt-cells = <1>;
325 device_type = "pci";
326 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
327 reg = <0xe0009000 0x00001000
328 0xb0000000 0x01000000>;
329 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
330 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
331 bus-range = <0 0>;
332 interrupt-map-mask = <0xf800 0 0 7>;
333 interrupt-map = <0 0 0 1 &ipic 1 8
334 0 0 0 2 &ipic 1 8
335 0 0 0 3 &ipic 1 8
336 0 0 0 4 &ipic 1 8>;
337 interrupts = <0x1 0x8>;
338 interrupt-parent = <&ipic>;
339 clock-frequency = <0>;
340
341 pcie@0 {
342 #address-cells = <3>;
343 #size-cells = <2>;
344 device_type = "pci";
345 reg = <0 0 0 0 0>;
346 ranges = <0x02000000 0 0xa0000000
347 0x02000000 0 0xa0000000
348 0 0x10000000
349 0x01000000 0 0x00000000
350 0x01000000 0 0x00000000
351 0 0x00800000>;
352 };
353 };
354};