Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 591a9634501eb27f32087018e815e11160a81133 / . / drivers / pinctrl / renesas / pfc-r8a7796.c
blob: a289397fb8f0385d7028323d94af27d73bbee2fe [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4 *
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6 *
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]12 */
13
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]14#include <dm.h>
15#include <errno.h>
16#include <dm/pinctrl.h>
17#include <linux/kernel.h>
18
19#include "sh_pfc.h"
20
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]21#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]22
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]23#define CPU_ALL_GP(fn, sfx) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]24 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]27 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]28 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]32 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]33 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]36
37#define CPU_ALL_NOGP(fn) \
38 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
57 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]72 PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]73 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
75 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
76 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
77 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
78 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
79 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
80 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
81
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]82/*
83 * F_() : just information
84 * FM() : macro for FN_xxx / xxx_MARK
85 */
86
87/* GPSR0 */
88#define GPSR0_15 F_(D15, IP7_11_8)
89#define GPSR0_14 F_(D14, IP7_7_4)
90#define GPSR0_13 F_(D13, IP7_3_0)
91#define GPSR0_12 F_(D12, IP6_31_28)
92#define GPSR0_11 F_(D11, IP6_27_24)
93#define GPSR0_10 F_(D10, IP6_23_20)
94#define GPSR0_9 F_(D9, IP6_19_16)
95#define GPSR0_8 F_(D8, IP6_15_12)
96#define GPSR0_7 F_(D7, IP6_11_8)
97#define GPSR0_6 F_(D6, IP6_7_4)
98#define GPSR0_5 F_(D5, IP6_3_0)
99#define GPSR0_4 F_(D4, IP5_31_28)
100#define GPSR0_3 F_(D3, IP5_27_24)
101#define GPSR0_2 F_(D2, IP5_23_20)
102#define GPSR0_1 F_(D1, IP5_19_16)
103#define GPSR0_0 F_(D0, IP5_15_12)
104
105/* GPSR1 */
106#define GPSR1_28 FM(CLKOUT)
107#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
108#define GPSR1_26 F_(WE1_N, IP5_7_4)
109#define GPSR1_25 F_(WE0_N, IP5_3_0)
110#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
111#define GPSR1_23 F_(RD_N, IP4_27_24)
112#define GPSR1_22 F_(BS_N, IP4_23_20)
113#define GPSR1_21 F_(CS1_N, IP4_19_16)
114#define GPSR1_20 F_(CS0_N, IP4_15_12)
115#define GPSR1_19 F_(A19, IP4_11_8)
116#define GPSR1_18 F_(A18, IP4_7_4)
117#define GPSR1_17 F_(A17, IP4_3_0)
118#define GPSR1_16 F_(A16, IP3_31_28)
119#define GPSR1_15 F_(A15, IP3_27_24)
120#define GPSR1_14 F_(A14, IP3_23_20)
121#define GPSR1_13 F_(A13, IP3_19_16)
122#define GPSR1_12 F_(A12, IP3_15_12)
123#define GPSR1_11 F_(A11, IP3_11_8)
124#define GPSR1_10 F_(A10, IP3_7_4)
125#define GPSR1_9 F_(A9, IP3_3_0)
126#define GPSR1_8 F_(A8, IP2_31_28)
127#define GPSR1_7 F_(A7, IP2_27_24)
128#define GPSR1_6 F_(A6, IP2_23_20)
129#define GPSR1_5 F_(A5, IP2_19_16)
130#define GPSR1_4 F_(A4, IP2_15_12)
131#define GPSR1_3 F_(A3, IP2_11_8)
132#define GPSR1_2 F_(A2, IP2_7_4)
133#define GPSR1_1 F_(A1, IP2_3_0)
134#define GPSR1_0 F_(A0, IP1_31_28)
135
136/* GPSR2 */
137#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
138#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
139#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
140#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
141#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
142#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
143#define GPSR2_8 F_(PWM2_A, IP1_27_24)
144#define GPSR2_7 F_(PWM1_A, IP1_23_20)
145#define GPSR2_6 F_(PWM0, IP1_19_16)
146#define GPSR2_5 F_(IRQ5, IP1_15_12)
147#define GPSR2_4 F_(IRQ4, IP1_11_8)
148#define GPSR2_3 F_(IRQ3, IP1_7_4)
149#define GPSR2_2 F_(IRQ2, IP1_3_0)
150#define GPSR2_1 F_(IRQ1, IP0_31_28)
151#define GPSR2_0 F_(IRQ0, IP0_27_24)
152
153/* GPSR3 */
154#define GPSR3_15 F_(SD1_WP, IP11_23_20)
155#define GPSR3_14 F_(SD1_CD, IP11_19_16)
156#define GPSR3_13 F_(SD0_WP, IP11_15_12)
157#define GPSR3_12 F_(SD0_CD, IP11_11_8)
158#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
159#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
160#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
161#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
162#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
163#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
164#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
165#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
166#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
167#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
168#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
169#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
170
171/* GPSR4 */
172#define GPSR4_17 F_(SD3_DS, IP11_7_4)
173#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
174#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
175#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
176#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
177#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
178#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
179#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
180#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
181#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
182#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
183#define GPSR4_6 F_(SD2_DS, IP9_27_24)
184#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
185#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
186#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
187#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
188#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
189#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
190
191/* GPSR5 */
192#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
193#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
194#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
195#define GPSR5_22 FM(MSIOF0_RXD)
196#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
197#define GPSR5_20 FM(MSIOF0_TXD)
198#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
199#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
200#define GPSR5_17 FM(MSIOF0_SCK)
201#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
202#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
203#define GPSR5_14 F_(HTX0, IP13_19_16)
204#define GPSR5_13 F_(HRX0, IP13_15_12)
205#define GPSR5_12 F_(HSCK0, IP13_11_8)
206#define GPSR5_11 F_(RX2_A, IP13_7_4)
207#define GPSR5_10 F_(TX2_A, IP13_3_0)
208#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]209#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]210#define GPSR5_7 F_(CTS1_N, IP12_23_20)
211#define GPSR5_6 F_(TX1_A, IP12_19_16)
212#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]213#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]214#define GPSR5_3 F_(CTS0_N, IP12_7_4)
215#define GPSR5_2 F_(TX0, IP12_3_0)
216#define GPSR5_1 F_(RX0, IP11_31_28)
217#define GPSR5_0 F_(SCK0, IP11_27_24)
218
219/* GPSR6 */
220#define GPSR6_31 F_(GP6_31, IP18_7_4)
221#define GPSR6_30 F_(GP6_30, IP18_3_0)
222#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
223#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
224#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
225#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
226#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
227#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
228#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
229#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
230#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
231#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
232#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
233#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
234#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
235#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
236#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
237#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
238#define GPSR6_13 FM(SSI_SDATA5)
239#define GPSR6_12 FM(SSI_WS5)
240#define GPSR6_11 FM(SSI_SCK5)
241#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
242#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
243#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
244#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
245#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
246#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
247#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
248#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
249#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
250#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
251#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
252
253/* GPSR7 */
254#define GPSR7_3 FM(GP7_03)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]255#define GPSR7_2 FM(GP7_02)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]256#define GPSR7_1 FM(AVS2)
257#define GPSR7_0 FM(AVS1)
258
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]259/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
260#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]265#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]266#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]269#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]275#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]285#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]286#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287
288/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
289#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]303#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]304#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]316#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]317#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318
319/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
320#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354
355/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
356#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]363#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]364#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]367#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]368#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
377#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384
385/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
386#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]403#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]404#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
406#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
407#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
408#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
409#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
410#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
412#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
413
414#define PINMUX_GPSR \
415\
416 GPSR6_31 \
417 GPSR6_30 \
418 GPSR6_29 \
419 GPSR1_28 GPSR6_28 \
420 GPSR1_27 GPSR6_27 \
421 GPSR1_26 GPSR6_26 \
422 GPSR1_25 GPSR5_25 GPSR6_25 \
423 GPSR1_24 GPSR5_24 GPSR6_24 \
424 GPSR1_23 GPSR5_23 GPSR6_23 \
425 GPSR1_22 GPSR5_22 GPSR6_22 \
426 GPSR1_21 GPSR5_21 GPSR6_21 \
427 GPSR1_20 GPSR5_20 GPSR6_20 \
428 GPSR1_19 GPSR5_19 GPSR6_19 \
429 GPSR1_18 GPSR5_18 GPSR6_18 \
430 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
431 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
432GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
433GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
434GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
435GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
436GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
437GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
438GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
439GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
440GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
441GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
442GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
443GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
444GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
445GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
446GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
447GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
448
449#define PINMUX_IPSR \
450\
451FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
452FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
453FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
454FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
455FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
456FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
457FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
458FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
459\
460FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
461FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
462FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
463FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
464FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
465FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
466FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
467FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
468\
469FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
470FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
471FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
472FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
473FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
474FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
475FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
476FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
477\
478FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
479FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
480FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
481FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
482FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
483FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
484FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
485FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
486\
487FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
488FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
489FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
490FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
491FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
492FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
493FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
494FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
495
496/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
497#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
498#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
499#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
500#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
501#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
502#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
503#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
504#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
505#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
506#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
507#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
508#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
509#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
510#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
511#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
512#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
513#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]514#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]515
516/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
517#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
518#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
519#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
520#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
521#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]522#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]523#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
524#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
525#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
526#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
527#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
528#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
529#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
530#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
531#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
532#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
533#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
534#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
535#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
536#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
537#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
538#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
539
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]540/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]541#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
542#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
543#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
544#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
545#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
546#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]547#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]548#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
549#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
550#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]551#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
552#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]553#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
554
555#define PINMUX_MOD_SELS \
556\
557MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
558 MOD_SEL2_30 \
559 MOD_SEL1_29_28_27 MOD_SEL2_29 \
560MOD_SEL0_28_27 MOD_SEL2_28_27 \
561MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
562 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
563MOD_SEL0_23 MOD_SEL1_23_22_21 \
564MOD_SEL0_22 MOD_SEL2_22 \
565MOD_SEL0_21 MOD_SEL2_21 \
566MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
567MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
568MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
569 MOD_SEL2_17 \
570MOD_SEL0_16 MOD_SEL1_16 \
571 MOD_SEL1_15_14 \
572MOD_SEL0_14_13 \
573 MOD_SEL1_13 \
574MOD_SEL0_12 MOD_SEL1_12 \
575MOD_SEL0_11 MOD_SEL1_11 \
576MOD_SEL0_10 MOD_SEL1_10 \
577MOD_SEL0_9_8 MOD_SEL1_9 \
578MOD_SEL0_7_6 \
579 MOD_SEL1_6 \
580MOD_SEL0_5 MOD_SEL1_5 \
581MOD_SEL0_4_3 MOD_SEL1_4 \
582 MOD_SEL1_3 \
583 MOD_SEL1_2 \
584 MOD_SEL1_1 \
585 MOD_SEL1_0 MOD_SEL2_0
586
587/*
588 * These pins are not able to be muxed but have other properties
589 * that can be set, such as drive-strength or pull-up/pull-down enable.
590 */
591#define PINMUX_STATIC \
592 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
593 FM(QSPI0_IO2) FM(QSPI0_IO3) \
594 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
595 FM(QSPI1_IO2) FM(QSPI1_IO3) \
596 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
597 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
598 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
599 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
600 FM(PRESETOUT) \
601 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
602 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
603
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]604#define PINMUX_PHYS \
605 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
606
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]607enum {
608 PINMUX_RESERVED = 0,
609
610 PINMUX_DATA_BEGIN,
611 GP_ALL(DATA),
612 PINMUX_DATA_END,
613
614#define F_(x, y)
615#define FM(x) FN_##x,
616 PINMUX_FUNCTION_BEGIN,
617 GP_ALL(FN),
618 PINMUX_GPSR
619 PINMUX_IPSR
620 PINMUX_MOD_SELS
621 PINMUX_FUNCTION_END,
622#undef F_
623#undef FM
624
625#define F_(x, y)
626#define FM(x) x##_MARK,
627 PINMUX_MARK_BEGIN,
628 PINMUX_GPSR
629 PINMUX_IPSR
630 PINMUX_MOD_SELS
631 PINMUX_STATIC
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]632 PINMUX_PHYS
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]633 PINMUX_MARK_END,
634#undef F_
635#undef FM
636};
637
638static const u16 pinmux_data[] = {
639 PINMUX_DATA_GP_ALL(),
640
641 PINMUX_SINGLE(AVS1),
642 PINMUX_SINGLE(AVS2),
643 PINMUX_SINGLE(CLKOUT),
644 PINMUX_SINGLE(GP7_03),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]645 PINMUX_SINGLE(GP7_02),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]646 PINMUX_SINGLE(MSIOF0_RXD),
647 PINMUX_SINGLE(MSIOF0_SCK),
648 PINMUX_SINGLE(MSIOF0_TXD),
649 PINMUX_SINGLE(SSI_SCK5),
650 PINMUX_SINGLE(SSI_SDATA5),
651 PINMUX_SINGLE(SSI_WS5),
652
653 /* IPSR0 */
654 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
655 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
656
657 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
658 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
659 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
660
661 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
662 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
663 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
664
665 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
666 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
667 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
668
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]669 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
672 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]673
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]674 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
677 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]678
679 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
680 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
681 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
682 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
683 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
685 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
686
687 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
688 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
689 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
690 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
693 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
694
695 /* IPSR1 */
696 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
697 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
698 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
699 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
700 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
701 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
702
703 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
704 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]705 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
706 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
707 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
708 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
709
710 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
711 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]712 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
713 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
714 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
715 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
716
717 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
718 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]719 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
720 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
721 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
722 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
723
724 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
725 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]726 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
727 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
728
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]729 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
730 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]733 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]734
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]735 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
736 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
738 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]739
740 PINMUX_IPSR_GPSR(IP1_31_28, A0),
741 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
742 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
743 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
744 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
745 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
746
747 /* IPSR2 */
748 PINMUX_IPSR_GPSR(IP2_3_0, A1),
749 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
750 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
751 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
752 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
753 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
754
755 PINMUX_IPSR_GPSR(IP2_7_4, A2),
756 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
757 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
758 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
759 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
760 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
761
762 PINMUX_IPSR_GPSR(IP2_11_8, A3),
763 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
764 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
765 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
766 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
767 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
768
769 PINMUX_IPSR_GPSR(IP2_15_12, A4),
770 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
771 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
772 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
773 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
774 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
775
776 PINMUX_IPSR_GPSR(IP2_19_16, A5),
777 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
778 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
779 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
780 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
781 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
782 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
783
784 PINMUX_IPSR_GPSR(IP2_23_20, A6),
785 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
786 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
787 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
788 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
789 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
790 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
791
792 PINMUX_IPSR_GPSR(IP2_27_24, A7),
793 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
794 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
795 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
796 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
797 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
798 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
799
800 PINMUX_IPSR_GPSR(IP2_31_28, A8),
801 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
802 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
803 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
804 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
805 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
806 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
807
808 /* IPSR3 */
809 PINMUX_IPSR_GPSR(IP3_3_0, A9),
810 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
811 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
812 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
813
814 PINMUX_IPSR_GPSR(IP3_7_4, A10),
815 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]816 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]817 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
818
819 PINMUX_IPSR_GPSR(IP3_11_8, A11),
820 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
821 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
822 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
823 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
824 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
825 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
826 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
827 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
828
829 PINMUX_IPSR_GPSR(IP3_15_12, A12),
830 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
831 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
832 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
833 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
834 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
835
836 PINMUX_IPSR_GPSR(IP3_19_16, A13),
837 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
838 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
839 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
840 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
841 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
842
843 PINMUX_IPSR_GPSR(IP3_23_20, A14),
844 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
845 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
846 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
847 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
848 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
849
850 PINMUX_IPSR_GPSR(IP3_27_24, A15),
851 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
852 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
853 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
854 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
855 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
856
857 PINMUX_IPSR_GPSR(IP3_31_28, A16),
858 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
859 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
860 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
861
862 /* IPSR4 */
863 PINMUX_IPSR_GPSR(IP4_3_0, A17),
864 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
865 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
866 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
867
868 PINMUX_IPSR_GPSR(IP4_7_4, A18),
869 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
870 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
871 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
872
873 PINMUX_IPSR_GPSR(IP4_11_8, A19),
874 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
875 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
876 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
877
878 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
879 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
880
881 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
882 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
883 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
884
885 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
886 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
887 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
888 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
889 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
890 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
891 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
892 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
893
894 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
895 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
896 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
897 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
898 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
899 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
900
901 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
902 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
903 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
904 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
905 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
906 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
907
908 /* IPSR5 */
909 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
910 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
911 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
912 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
913 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
914 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
915 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
916
917 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
918 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]919 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]920 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
921 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
922 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
923 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
924 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
925
926 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
927 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
928 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
929 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
930
931 PINMUX_IPSR_GPSR(IP5_15_12, D0),
932 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
933 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
934 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
935 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
936
937 PINMUX_IPSR_GPSR(IP5_19_16, D1),
938 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
939 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
940 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
941 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
942
943 PINMUX_IPSR_GPSR(IP5_23_20, D2),
944 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
945 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
946 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
947
948 PINMUX_IPSR_GPSR(IP5_27_24, D3),
949 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
950 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
951 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
952
953 PINMUX_IPSR_GPSR(IP5_31_28, D4),
954 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
955 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
956 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
957
958 /* IPSR6 */
959 PINMUX_IPSR_GPSR(IP6_3_0, D5),
960 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
961 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
962 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
963
964 PINMUX_IPSR_GPSR(IP6_7_4, D6),
965 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
966 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
967 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
968
969 PINMUX_IPSR_GPSR(IP6_11_8, D7),
970 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
971 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
972 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
973
974 PINMUX_IPSR_GPSR(IP6_15_12, D8),
975 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
976 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
977 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
978 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
979 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
980
981 PINMUX_IPSR_GPSR(IP6_19_16, D9),
982 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
983 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
984 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
985 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
986
987 PINMUX_IPSR_GPSR(IP6_23_20, D10),
988 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
989 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
990 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
991 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
992 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
993 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
994
995 PINMUX_IPSR_GPSR(IP6_27_24, D11),
996 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
997 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
998 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
999 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1000 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1001 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1002
1003 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1004 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1005 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1006 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1007 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1008 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1009
1010 /* IPSR7 */
1011 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1012 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1013 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1014 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1015 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1016 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1017
1018 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1019 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1020 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1021 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1022 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1023 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1024 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1025
1026 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1027 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1028 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1029 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1030 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1031 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1032 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1033
1034 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1035 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1036 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1037
1038 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1039 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1040 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1041
1042 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1043 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1044 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1045 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1046
1047 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1048 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1049 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1050 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1051
1052 /* IPSR8 */
1053 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1054 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1055 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1056 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1057
1058 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1059 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1060 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1061 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1062
1063 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1064 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1065 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1066
1067 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1068 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1069 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1070 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1071 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1072
1073 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1074 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1075 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1076 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1077 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1078 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1079
1080 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1081 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1082 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1083 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1084 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1085 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1086
1087 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1088 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1089 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1090 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1091 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1092 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1093
1094 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1095 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1096 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1097 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1098 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1099 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1100
1101 /* IPSR9 */
1102 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1103 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1104
1105 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1106 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1107
1108 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1109 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1110
1111 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1112 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1113
1114 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1115 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1116
1117 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1118 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1119
1120 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1121 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1122
1123 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1124 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1125
1126 /* IPSR10 */
1127 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1128 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1129
1130 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1131 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1132
1133 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1134 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1135
1136 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1137 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1138
1139 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1140 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1141
1142 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1143 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1144 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1145
1146 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1147 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1148 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1149
1150 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1151 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1152 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1153
1154 /* IPSR11 */
1155 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1156 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1157 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1158
1159 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1160 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1161
1162 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1163 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1164 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1165 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1166
1167 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1168 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1169 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1170
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1171 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1172 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1173 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1174 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1175
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1176 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1177 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1178 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1179 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1180
1181 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1182 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1183 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1184 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1185 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1186 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1187 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1188 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1189 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1190 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1191
1192 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1193 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1194 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1195 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1196 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1197
1198 /* IPSR12 */
1199 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1200 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1201 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1202 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1203 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1204
1205 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1206 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1207 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1208 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1209 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1210 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1211 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1212 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1213
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1214 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1215 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1216 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1217 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1218 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1219 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1220 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1221 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1222
1223 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1224 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1225 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1226 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1227 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1228
1229 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1230 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1231 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1232 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1233 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1234
1235 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1236 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1237 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1238 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1239 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1240 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1241 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1242
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1243 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1244 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1245 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1246 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1247 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1248 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1249 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1250
1251 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1252 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1253 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1254 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1255 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1256 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1257 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1258
1259 /* IPSR13 */
1260 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1261 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1262 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1263 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1264 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1265 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1266
1267 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1268 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1269 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1270 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1271 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1272 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1273
1274 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1275 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1276 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1277 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1278 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1279 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1280 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1281 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1282
1283 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1284 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1285 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1286 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1287 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1288 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1289
1290 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1291 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1292 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1293 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1294 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1295 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1296
1297 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1298 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1299 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1300 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1301 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1302 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1303 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1304 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1305
1306 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1307 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1308 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1309 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1310 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1311 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1312 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1313
1314 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1315 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1316 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1317 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1318
1319 /* IPSR14 */
1320 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1321 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1322 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1323 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1324 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1325 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1326 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1327 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1328
1329 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1330 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1331 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1332 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1333 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1334 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1335 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1336 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1337
1338 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1339 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1340 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1341
1342 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1343 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1344 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1345 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1346
1347 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1348 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1349 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1350
1351 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1352 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1353
1354 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1355 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1356
1357 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1358 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1359
1360 /* IPSR15 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1361 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1362
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1363 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1364 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1365
1366 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1367 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1368 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1369
1370 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1371 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1372 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1373 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1374
1375 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1376 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1377 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1378 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1379 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1380 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1381 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1382
1383 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1384 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1385 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1386 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1387 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1388 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1389 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1390
1391 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1392 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1393 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1394 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1395 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1396 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1397 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1398
1399 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1400 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1401 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1402 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1403 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1404 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1405 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1406
1407 /* IPSR16 */
1408 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1409 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1410
1411 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1412 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1413
1414 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1415 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1416
1417 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1418 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1419 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1420 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1421 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1422 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1423 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1424
1425 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1426 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1427 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1428 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1429 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1430 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1431 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1432
1433 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1434 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1435 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1436 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1437 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1438 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1439 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1440 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1441
1442 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1443 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1444 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1445 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1446 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1447 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1448 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1449
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1450 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1451 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1452 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1453 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1454 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1455 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1456 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1457 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1458
1459 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1460 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1461
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1462 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1463 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1464 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1465 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1466 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1467
1468 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1469 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1470 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1471 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1472 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1473 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1474 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1475
1476 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1477 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1478 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1479 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1480 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1481 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1482
1483 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1484 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1485 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1486 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1487 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1488 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1489 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1490 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1491 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1492
1493 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1494 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1495 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1496 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1497 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1498 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1499 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1500 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1501 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1502
1503 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1504 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1505 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1506 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1507 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1508 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1509 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1510 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1511 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1512 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1513 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1514
1515 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1516 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1517 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1518 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1519 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1520 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1521 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1522 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1523 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1524
1525 /* IPSR18 */
1526 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1527 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1528 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1529 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1530 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1531 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1532 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1533 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1534 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1535
1536 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1537 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1538 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1539 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1540 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1541 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1542 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1543 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1544 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1545
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1546/*
1547 * Static pins can not be muxed between different functions but
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1548 * still need mark entries in the pinmux list. Add each static
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1549 * pin to the list without an associated function. The sh-pfc
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1550 * core will do the right thing and skip trying to mux the pin
1551 * while still applying configuration to it.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1552 */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]1553#define FM(x) PINMUX_DATA(x##_MARK, 0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1554 PINMUX_STATIC
1555#undef FM
1556};
1557
1558/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1559 * Pins not associated with a GPIO port.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1560 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1561enum {
1562 GP_ASSIGN_LAST(),
1563 NOGP_ALL(),
1564};
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1565
1566static const struct sh_pfc_pin pinmux_pins[] = {
1567 PINMUX_GPIO_GP_ALL(),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1568 PINMUX_NOGP_ALL(),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1569};
1570
1571/* - AUDIO CLOCK ------------------------------------------------------------ */
1572static const unsigned int audio_clk_a_a_pins[] = {
1573 /* CLK A */
1574 RCAR_GP_PIN(6, 22),
1575};
1576static const unsigned int audio_clk_a_a_mux[] = {
1577 AUDIO_CLKA_A_MARK,
1578};
1579static const unsigned int audio_clk_a_b_pins[] = {
1580 /* CLK A */
1581 RCAR_GP_PIN(5, 4),
1582};
1583static const unsigned int audio_clk_a_b_mux[] = {
1584 AUDIO_CLKA_B_MARK,
1585};
1586static const unsigned int audio_clk_a_c_pins[] = {
1587 /* CLK A */
1588 RCAR_GP_PIN(5, 19),
1589};
1590static const unsigned int audio_clk_a_c_mux[] = {
1591 AUDIO_CLKA_C_MARK,
1592};
1593static const unsigned int audio_clk_b_a_pins[] = {
1594 /* CLK B */
1595 RCAR_GP_PIN(5, 12),
1596};
1597static const unsigned int audio_clk_b_a_mux[] = {
1598 AUDIO_CLKB_A_MARK,
1599};
1600static const unsigned int audio_clk_b_b_pins[] = {
1601 /* CLK B */
1602 RCAR_GP_PIN(6, 23),
1603};
1604static const unsigned int audio_clk_b_b_mux[] = {
1605 AUDIO_CLKB_B_MARK,
1606};
1607static const unsigned int audio_clk_c_a_pins[] = {
1608 /* CLK C */
1609 RCAR_GP_PIN(5, 21),
1610};
1611static const unsigned int audio_clk_c_a_mux[] = {
1612 AUDIO_CLKC_A_MARK,
1613};
1614static const unsigned int audio_clk_c_b_pins[] = {
1615 /* CLK C */
1616 RCAR_GP_PIN(5, 0),
1617};
1618static const unsigned int audio_clk_c_b_mux[] = {
1619 AUDIO_CLKC_B_MARK,
1620};
1621static const unsigned int audio_clkout_a_pins[] = {
1622 /* CLKOUT */
1623 RCAR_GP_PIN(5, 18),
1624};
1625static const unsigned int audio_clkout_a_mux[] = {
1626 AUDIO_CLKOUT_A_MARK,
1627};
1628static const unsigned int audio_clkout_b_pins[] = {
1629 /* CLKOUT */
1630 RCAR_GP_PIN(6, 28),
1631};
1632static const unsigned int audio_clkout_b_mux[] = {
1633 AUDIO_CLKOUT_B_MARK,
1634};
1635static const unsigned int audio_clkout_c_pins[] = {
1636 /* CLKOUT */
1637 RCAR_GP_PIN(5, 3),
1638};
1639static const unsigned int audio_clkout_c_mux[] = {
1640 AUDIO_CLKOUT_C_MARK,
1641};
1642static const unsigned int audio_clkout_d_pins[] = {
1643 /* CLKOUT */
1644 RCAR_GP_PIN(5, 21),
1645};
1646static const unsigned int audio_clkout_d_mux[] = {
1647 AUDIO_CLKOUT_D_MARK,
1648};
1649static const unsigned int audio_clkout1_a_pins[] = {
1650 /* CLKOUT1 */
1651 RCAR_GP_PIN(5, 15),
1652};
1653static const unsigned int audio_clkout1_a_mux[] = {
1654 AUDIO_CLKOUT1_A_MARK,
1655};
1656static const unsigned int audio_clkout1_b_pins[] = {
1657 /* CLKOUT1 */
1658 RCAR_GP_PIN(6, 29),
1659};
1660static const unsigned int audio_clkout1_b_mux[] = {
1661 AUDIO_CLKOUT1_B_MARK,
1662};
1663static const unsigned int audio_clkout2_a_pins[] = {
1664 /* CLKOUT2 */
1665 RCAR_GP_PIN(5, 16),
1666};
1667static const unsigned int audio_clkout2_a_mux[] = {
1668 AUDIO_CLKOUT2_A_MARK,
1669};
1670static const unsigned int audio_clkout2_b_pins[] = {
1671 /* CLKOUT2 */
1672 RCAR_GP_PIN(6, 30),
1673};
1674static const unsigned int audio_clkout2_b_mux[] = {
1675 AUDIO_CLKOUT2_B_MARK,
1676};
1677
1678static const unsigned int audio_clkout3_a_pins[] = {
1679 /* CLKOUT3 */
1680 RCAR_GP_PIN(5, 19),
1681};
1682static const unsigned int audio_clkout3_a_mux[] = {
1683 AUDIO_CLKOUT3_A_MARK,
1684};
1685static const unsigned int audio_clkout3_b_pins[] = {
1686 /* CLKOUT3 */
1687 RCAR_GP_PIN(6, 31),
1688};
1689static const unsigned int audio_clkout3_b_mux[] = {
1690 AUDIO_CLKOUT3_B_MARK,
1691};
1692
1693/* - EtherAVB --------------------------------------------------------------- */
1694static const unsigned int avb_link_pins[] = {
1695 /* AVB_LINK */
1696 RCAR_GP_PIN(2, 12),
1697};
1698static const unsigned int avb_link_mux[] = {
1699 AVB_LINK_MARK,
1700};
1701static const unsigned int avb_magic_pins[] = {
1702 /* AVB_MAGIC_ */
1703 RCAR_GP_PIN(2, 10),
1704};
1705static const unsigned int avb_magic_mux[] = {
1706 AVB_MAGIC_MARK,
1707};
1708static const unsigned int avb_phy_int_pins[] = {
1709 /* AVB_PHY_INT */
1710 RCAR_GP_PIN(2, 11),
1711};
1712static const unsigned int avb_phy_int_mux[] = {
1713 AVB_PHY_INT_MARK,
1714};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1715static const unsigned int avb_mdio_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1716 /* AVB_MDC, AVB_MDIO */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1717 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1718};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1719static const unsigned int avb_mdio_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1720 AVB_MDC_MARK, AVB_MDIO_MARK,
1721};
1722static const unsigned int avb_mii_pins[] = {
1723 /*
1724 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1725 * AVB_TD1, AVB_TD2, AVB_TD3,
1726 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1727 * AVB_RD1, AVB_RD2, AVB_RD3,
1728 * AVB_TXCREFCLK
1729 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1730 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1731 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1732 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1733 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1734 PIN_AVB_TXCREFCLK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1735};
1736static const unsigned int avb_mii_mux[] = {
1737 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1738 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1739 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1740 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1741 AVB_TXCREFCLK_MARK,
1742};
1743static const unsigned int avb_avtp_pps_pins[] = {
1744 /* AVB_AVTP_PPS */
1745 RCAR_GP_PIN(2, 6),
1746};
1747static const unsigned int avb_avtp_pps_mux[] = {
1748 AVB_AVTP_PPS_MARK,
1749};
1750static const unsigned int avb_avtp_match_a_pins[] = {
1751 /* AVB_AVTP_MATCH_A */
1752 RCAR_GP_PIN(2, 13),
1753};
1754static const unsigned int avb_avtp_match_a_mux[] = {
1755 AVB_AVTP_MATCH_A_MARK,
1756};
1757static const unsigned int avb_avtp_capture_a_pins[] = {
1758 /* AVB_AVTP_CAPTURE_A */
1759 RCAR_GP_PIN(2, 14),
1760};
1761static const unsigned int avb_avtp_capture_a_mux[] = {
1762 AVB_AVTP_CAPTURE_A_MARK,
1763};
1764static const unsigned int avb_avtp_match_b_pins[] = {
1765 /* AVB_AVTP_MATCH_B */
1766 RCAR_GP_PIN(1, 8),
1767};
1768static const unsigned int avb_avtp_match_b_mux[] = {
1769 AVB_AVTP_MATCH_B_MARK,
1770};
1771static const unsigned int avb_avtp_capture_b_pins[] = {
1772 /* AVB_AVTP_CAPTURE_B */
1773 RCAR_GP_PIN(1, 11),
1774};
1775static const unsigned int avb_avtp_capture_b_mux[] = {
1776 AVB_AVTP_CAPTURE_B_MARK,
1777};
1778
1779/* - CAN ------------------------------------------------------------------ */
1780static const unsigned int can0_data_a_pins[] = {
1781 /* TX, RX */
1782 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1783};
1784static const unsigned int can0_data_a_mux[] = {
1785 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1786};
1787static const unsigned int can0_data_b_pins[] = {
1788 /* TX, RX */
1789 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1790};
1791static const unsigned int can0_data_b_mux[] = {
1792 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1793};
1794static const unsigned int can1_data_pins[] = {
1795 /* TX, RX */
1796 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1797};
1798static const unsigned int can1_data_mux[] = {
1799 CAN1_TX_MARK, CAN1_RX_MARK,
1800};
1801
1802/* - CAN Clock -------------------------------------------------------------- */
1803static const unsigned int can_clk_pins[] = {
1804 /* CLK */
1805 RCAR_GP_PIN(1, 25),
1806};
1807static const unsigned int can_clk_mux[] = {
1808 CAN_CLK_MARK,
1809};
1810
1811/* - CAN FD --------------------------------------------------------------- */
1812static const unsigned int canfd0_data_a_pins[] = {
1813 /* TX, RX */
1814 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1815};
1816static const unsigned int canfd0_data_a_mux[] = {
1817 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1818};
1819static const unsigned int canfd0_data_b_pins[] = {
1820 /* TX, RX */
1821 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1822};
1823static const unsigned int canfd0_data_b_mux[] = {
1824 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1825};
1826static const unsigned int canfd1_data_pins[] = {
1827 /* TX, RX */
1828 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1829};
1830static const unsigned int canfd1_data_mux[] = {
1831 CANFD1_TX_MARK, CANFD1_RX_MARK,
1832};
1833
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]1834#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1835/* - DRIF0 --------------------------------------------------------------- */
1836static const unsigned int drif0_ctrl_a_pins[] = {
1837 /* CLK, SYNC */
1838 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1839};
1840static const unsigned int drif0_ctrl_a_mux[] = {
1841 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1842};
1843static const unsigned int drif0_data0_a_pins[] = {
1844 /* D0 */
1845 RCAR_GP_PIN(6, 10),
1846};
1847static const unsigned int drif0_data0_a_mux[] = {
1848 RIF0_D0_A_MARK,
1849};
1850static const unsigned int drif0_data1_a_pins[] = {
1851 /* D1 */
1852 RCAR_GP_PIN(6, 7),
1853};
1854static const unsigned int drif0_data1_a_mux[] = {
1855 RIF0_D1_A_MARK,
1856};
1857static const unsigned int drif0_ctrl_b_pins[] = {
1858 /* CLK, SYNC */
1859 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1860};
1861static const unsigned int drif0_ctrl_b_mux[] = {
1862 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1863};
1864static const unsigned int drif0_data0_b_pins[] = {
1865 /* D0 */
1866 RCAR_GP_PIN(5, 1),
1867};
1868static const unsigned int drif0_data0_b_mux[] = {
1869 RIF0_D0_B_MARK,
1870};
1871static const unsigned int drif0_data1_b_pins[] = {
1872 /* D1 */
1873 RCAR_GP_PIN(5, 2),
1874};
1875static const unsigned int drif0_data1_b_mux[] = {
1876 RIF0_D1_B_MARK,
1877};
1878static const unsigned int drif0_ctrl_c_pins[] = {
1879 /* CLK, SYNC */
1880 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1881};
1882static const unsigned int drif0_ctrl_c_mux[] = {
1883 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1884};
1885static const unsigned int drif0_data0_c_pins[] = {
1886 /* D0 */
1887 RCAR_GP_PIN(5, 13),
1888};
1889static const unsigned int drif0_data0_c_mux[] = {
1890 RIF0_D0_C_MARK,
1891};
1892static const unsigned int drif0_data1_c_pins[] = {
1893 /* D1 */
1894 RCAR_GP_PIN(5, 14),
1895};
1896static const unsigned int drif0_data1_c_mux[] = {
1897 RIF0_D1_C_MARK,
1898};
1899/* - DRIF1 --------------------------------------------------------------- */
1900static const unsigned int drif1_ctrl_a_pins[] = {
1901 /* CLK, SYNC */
1902 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1903};
1904static const unsigned int drif1_ctrl_a_mux[] = {
1905 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1906};
1907static const unsigned int drif1_data0_a_pins[] = {
1908 /* D0 */
1909 RCAR_GP_PIN(6, 19),
1910};
1911static const unsigned int drif1_data0_a_mux[] = {
1912 RIF1_D0_A_MARK,
1913};
1914static const unsigned int drif1_data1_a_pins[] = {
1915 /* D1 */
1916 RCAR_GP_PIN(6, 20),
1917};
1918static const unsigned int drif1_data1_a_mux[] = {
1919 RIF1_D1_A_MARK,
1920};
1921static const unsigned int drif1_ctrl_b_pins[] = {
1922 /* CLK, SYNC */
1923 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1924};
1925static const unsigned int drif1_ctrl_b_mux[] = {
1926 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1927};
1928static const unsigned int drif1_data0_b_pins[] = {
1929 /* D0 */
1930 RCAR_GP_PIN(5, 7),
1931};
1932static const unsigned int drif1_data0_b_mux[] = {
1933 RIF1_D0_B_MARK,
1934};
1935static const unsigned int drif1_data1_b_pins[] = {
1936 /* D1 */
1937 RCAR_GP_PIN(5, 8),
1938};
1939static const unsigned int drif1_data1_b_mux[] = {
1940 RIF1_D1_B_MARK,
1941};
1942static const unsigned int drif1_ctrl_c_pins[] = {
1943 /* CLK, SYNC */
1944 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1945};
1946static const unsigned int drif1_ctrl_c_mux[] = {
1947 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1948};
1949static const unsigned int drif1_data0_c_pins[] = {
1950 /* D0 */
1951 RCAR_GP_PIN(5, 6),
1952};
1953static const unsigned int drif1_data0_c_mux[] = {
1954 RIF1_D0_C_MARK,
1955};
1956static const unsigned int drif1_data1_c_pins[] = {
1957 /* D1 */
1958 RCAR_GP_PIN(5, 10),
1959};
1960static const unsigned int drif1_data1_c_mux[] = {
1961 RIF1_D1_C_MARK,
1962};
1963/* - DRIF2 --------------------------------------------------------------- */
1964static const unsigned int drif2_ctrl_a_pins[] = {
1965 /* CLK, SYNC */
1966 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1967};
1968static const unsigned int drif2_ctrl_a_mux[] = {
1969 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1970};
1971static const unsigned int drif2_data0_a_pins[] = {
1972 /* D0 */
1973 RCAR_GP_PIN(6, 7),
1974};
1975static const unsigned int drif2_data0_a_mux[] = {
1976 RIF2_D0_A_MARK,
1977};
1978static const unsigned int drif2_data1_a_pins[] = {
1979 /* D1 */
1980 RCAR_GP_PIN(6, 10),
1981};
1982static const unsigned int drif2_data1_a_mux[] = {
1983 RIF2_D1_A_MARK,
1984};
1985static const unsigned int drif2_ctrl_b_pins[] = {
1986 /* CLK, SYNC */
1987 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1988};
1989static const unsigned int drif2_ctrl_b_mux[] = {
1990 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1991};
1992static const unsigned int drif2_data0_b_pins[] = {
1993 /* D0 */
1994 RCAR_GP_PIN(6, 30),
1995};
1996static const unsigned int drif2_data0_b_mux[] = {
1997 RIF2_D0_B_MARK,
1998};
1999static const unsigned int drif2_data1_b_pins[] = {
2000 /* D1 */
2001 RCAR_GP_PIN(6, 31),
2002};
2003static const unsigned int drif2_data1_b_mux[] = {
2004 RIF2_D1_B_MARK,
2005};
2006/* - DRIF3 --------------------------------------------------------------- */
2007static const unsigned int drif3_ctrl_a_pins[] = {
2008 /* CLK, SYNC */
2009 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2010};
2011static const unsigned int drif3_ctrl_a_mux[] = {
2012 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2013};
2014static const unsigned int drif3_data0_a_pins[] = {
2015 /* D0 */
2016 RCAR_GP_PIN(6, 19),
2017};
2018static const unsigned int drif3_data0_a_mux[] = {
2019 RIF3_D0_A_MARK,
2020};
2021static const unsigned int drif3_data1_a_pins[] = {
2022 /* D1 */
2023 RCAR_GP_PIN(6, 20),
2024};
2025static const unsigned int drif3_data1_a_mux[] = {
2026 RIF3_D1_A_MARK,
2027};
2028static const unsigned int drif3_ctrl_b_pins[] = {
2029 /* CLK, SYNC */
2030 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2031};
2032static const unsigned int drif3_ctrl_b_mux[] = {
2033 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2034};
2035static const unsigned int drif3_data0_b_pins[] = {
2036 /* D0 */
2037 RCAR_GP_PIN(6, 28),
2038};
2039static const unsigned int drif3_data0_b_mux[] = {
2040 RIF3_D0_B_MARK,
2041};
2042static const unsigned int drif3_data1_b_pins[] = {
2043 /* D1 */
2044 RCAR_GP_PIN(6, 29),
2045};
2046static const unsigned int drif3_data1_b_mux[] = {
2047 RIF3_D1_B_MARK,
2048};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]2049#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2050
2051/* - DU --------------------------------------------------------------------- */
2052static const unsigned int du_rgb666_pins[] = {
2053 /* R[7:2], G[7:2], B[7:2] */
2054 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2055 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2056 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2057 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2058 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2059 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2060};
2061static const unsigned int du_rgb666_mux[] = {
2062 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2063 DU_DR3_MARK, DU_DR2_MARK,
2064 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2065 DU_DG3_MARK, DU_DG2_MARK,
2066 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2067 DU_DB3_MARK, DU_DB2_MARK,
2068};
2069static const unsigned int du_rgb888_pins[] = {
2070 /* R[7:0], G[7:0], B[7:0] */
2071 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2072 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2073 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2074 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2075 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2076 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2077 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2078 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2079 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2080};
2081static const unsigned int du_rgb888_mux[] = {
2082 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2083 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2084 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2085 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2086 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2087 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2088};
2089static const unsigned int du_clk_out_0_pins[] = {
2090 /* CLKOUT */
2091 RCAR_GP_PIN(1, 27),
2092};
2093static const unsigned int du_clk_out_0_mux[] = {
2094 DU_DOTCLKOUT0_MARK
2095};
2096static const unsigned int du_clk_out_1_pins[] = {
2097 /* CLKOUT */
2098 RCAR_GP_PIN(2, 3),
2099};
2100static const unsigned int du_clk_out_1_mux[] = {
2101 DU_DOTCLKOUT1_MARK
2102};
2103static const unsigned int du_sync_pins[] = {
2104 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2105 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2106};
2107static const unsigned int du_sync_mux[] = {
2108 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2109};
2110static const unsigned int du_oddf_pins[] = {
2111 /* EXDISP/EXODDF/EXCDE */
2112 RCAR_GP_PIN(2, 2),
2113};
2114static const unsigned int du_oddf_mux[] = {
2115 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2116};
2117static const unsigned int du_cde_pins[] = {
2118 /* CDE */
2119 RCAR_GP_PIN(2, 0),
2120};
2121static const unsigned int du_cde_mux[] = {
2122 DU_CDE_MARK,
2123};
2124static const unsigned int du_disp_pins[] = {
2125 /* DISP */
2126 RCAR_GP_PIN(2, 1),
2127};
2128static const unsigned int du_disp_mux[] = {
2129 DU_DISP_MARK,
2130};
2131
2132/* - HSCIF0 ----------------------------------------------------------------- */
2133static const unsigned int hscif0_data_pins[] = {
2134 /* RX, TX */
2135 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2136};
2137static const unsigned int hscif0_data_mux[] = {
2138 HRX0_MARK, HTX0_MARK,
2139};
2140static const unsigned int hscif0_clk_pins[] = {
2141 /* SCK */
2142 RCAR_GP_PIN(5, 12),
2143};
2144static const unsigned int hscif0_clk_mux[] = {
2145 HSCK0_MARK,
2146};
2147static const unsigned int hscif0_ctrl_pins[] = {
2148 /* RTS, CTS */
2149 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2150};
2151static const unsigned int hscif0_ctrl_mux[] = {
2152 HRTS0_N_MARK, HCTS0_N_MARK,
2153};
2154/* - HSCIF1 ----------------------------------------------------------------- */
2155static const unsigned int hscif1_data_a_pins[] = {
2156 /* RX, TX */
2157 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2158};
2159static const unsigned int hscif1_data_a_mux[] = {
2160 HRX1_A_MARK, HTX1_A_MARK,
2161};
2162static const unsigned int hscif1_clk_a_pins[] = {
2163 /* SCK */
2164 RCAR_GP_PIN(6, 21),
2165};
2166static const unsigned int hscif1_clk_a_mux[] = {
2167 HSCK1_A_MARK,
2168};
2169static const unsigned int hscif1_ctrl_a_pins[] = {
2170 /* RTS, CTS */
2171 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2172};
2173static const unsigned int hscif1_ctrl_a_mux[] = {
2174 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2175};
2176
2177static const unsigned int hscif1_data_b_pins[] = {
2178 /* RX, TX */
2179 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2180};
2181static const unsigned int hscif1_data_b_mux[] = {
2182 HRX1_B_MARK, HTX1_B_MARK,
2183};
2184static const unsigned int hscif1_clk_b_pins[] = {
2185 /* SCK */
2186 RCAR_GP_PIN(5, 0),
2187};
2188static const unsigned int hscif1_clk_b_mux[] = {
2189 HSCK1_B_MARK,
2190};
2191static const unsigned int hscif1_ctrl_b_pins[] = {
2192 /* RTS, CTS */
2193 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2194};
2195static const unsigned int hscif1_ctrl_b_mux[] = {
2196 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2197};
2198/* - HSCIF2 ----------------------------------------------------------------- */
2199static const unsigned int hscif2_data_a_pins[] = {
2200 /* RX, TX */
2201 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2202};
2203static const unsigned int hscif2_data_a_mux[] = {
2204 HRX2_A_MARK, HTX2_A_MARK,
2205};
2206static const unsigned int hscif2_clk_a_pins[] = {
2207 /* SCK */
2208 RCAR_GP_PIN(6, 10),
2209};
2210static const unsigned int hscif2_clk_a_mux[] = {
2211 HSCK2_A_MARK,
2212};
2213static const unsigned int hscif2_ctrl_a_pins[] = {
2214 /* RTS, CTS */
2215 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2216};
2217static const unsigned int hscif2_ctrl_a_mux[] = {
2218 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2219};
2220
2221static const unsigned int hscif2_data_b_pins[] = {
2222 /* RX, TX */
2223 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2224};
2225static const unsigned int hscif2_data_b_mux[] = {
2226 HRX2_B_MARK, HTX2_B_MARK,
2227};
2228static const unsigned int hscif2_clk_b_pins[] = {
2229 /* SCK */
2230 RCAR_GP_PIN(6, 21),
2231};
2232static const unsigned int hscif2_clk_b_mux[] = {
2233 HSCK2_B_MARK,
2234};
2235static const unsigned int hscif2_ctrl_b_pins[] = {
2236 /* RTS, CTS */
2237 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2238};
2239static const unsigned int hscif2_ctrl_b_mux[] = {
2240 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2241};
2242
2243static const unsigned int hscif2_data_c_pins[] = {
2244 /* RX, TX */
2245 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2246};
2247static const unsigned int hscif2_data_c_mux[] = {
2248 HRX2_C_MARK, HTX2_C_MARK,
2249};
2250static const unsigned int hscif2_clk_c_pins[] = {
2251 /* SCK */
2252 RCAR_GP_PIN(6, 24),
2253};
2254static const unsigned int hscif2_clk_c_mux[] = {
2255 HSCK2_C_MARK,
2256};
2257static const unsigned int hscif2_ctrl_c_pins[] = {
2258 /* RTS, CTS */
2259 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2260};
2261static const unsigned int hscif2_ctrl_c_mux[] = {
2262 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2263};
2264/* - HSCIF3 ----------------------------------------------------------------- */
2265static const unsigned int hscif3_data_a_pins[] = {
2266 /* RX, TX */
2267 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2268};
2269static const unsigned int hscif3_data_a_mux[] = {
2270 HRX3_A_MARK, HTX3_A_MARK,
2271};
2272static const unsigned int hscif3_clk_pins[] = {
2273 /* SCK */
2274 RCAR_GP_PIN(1, 22),
2275};
2276static const unsigned int hscif3_clk_mux[] = {
2277 HSCK3_MARK,
2278};
2279static const unsigned int hscif3_ctrl_pins[] = {
2280 /* RTS, CTS */
2281 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2282};
2283static const unsigned int hscif3_ctrl_mux[] = {
2284 HRTS3_N_MARK, HCTS3_N_MARK,
2285};
2286
2287static const unsigned int hscif3_data_b_pins[] = {
2288 /* RX, TX */
2289 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2290};
2291static const unsigned int hscif3_data_b_mux[] = {
2292 HRX3_B_MARK, HTX3_B_MARK,
2293};
2294static const unsigned int hscif3_data_c_pins[] = {
2295 /* RX, TX */
2296 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2297};
2298static const unsigned int hscif3_data_c_mux[] = {
2299 HRX3_C_MARK, HTX3_C_MARK,
2300};
2301static const unsigned int hscif3_data_d_pins[] = {
2302 /* RX, TX */
2303 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2304};
2305static const unsigned int hscif3_data_d_mux[] = {
2306 HRX3_D_MARK, HTX3_D_MARK,
2307};
2308/* - HSCIF4 ----------------------------------------------------------------- */
2309static const unsigned int hscif4_data_a_pins[] = {
2310 /* RX, TX */
2311 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2312};
2313static const unsigned int hscif4_data_a_mux[] = {
2314 HRX4_A_MARK, HTX4_A_MARK,
2315};
2316static const unsigned int hscif4_clk_pins[] = {
2317 /* SCK */
2318 RCAR_GP_PIN(1, 11),
2319};
2320static const unsigned int hscif4_clk_mux[] = {
2321 HSCK4_MARK,
2322};
2323static const unsigned int hscif4_ctrl_pins[] = {
2324 /* RTS, CTS */
2325 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2326};
2327static const unsigned int hscif4_ctrl_mux[] = {
2328 HRTS4_N_MARK, HCTS4_N_MARK,
2329};
2330
2331static const unsigned int hscif4_data_b_pins[] = {
2332 /* RX, TX */
2333 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2334};
2335static const unsigned int hscif4_data_b_mux[] = {
2336 HRX4_B_MARK, HTX4_B_MARK,
2337};
2338
2339/* - I2C -------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2340static const unsigned int i2c0_pins[] = {
2341 /* SCL, SDA */
2342 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2343};
2344
2345static const unsigned int i2c0_mux[] = {
2346 SCL0_MARK, SDA0_MARK,
2347};
2348
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2349static const unsigned int i2c1_a_pins[] = {
2350 /* SDA, SCL */
2351 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2352};
2353static const unsigned int i2c1_a_mux[] = {
2354 SDA1_A_MARK, SCL1_A_MARK,
2355};
2356static const unsigned int i2c1_b_pins[] = {
2357 /* SDA, SCL */
2358 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2359};
2360static const unsigned int i2c1_b_mux[] = {
2361 SDA1_B_MARK, SCL1_B_MARK,
2362};
2363static const unsigned int i2c2_a_pins[] = {
2364 /* SDA, SCL */
2365 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2366};
2367static const unsigned int i2c2_a_mux[] = {
2368 SDA2_A_MARK, SCL2_A_MARK,
2369};
2370static const unsigned int i2c2_b_pins[] = {
2371 /* SDA, SCL */
2372 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2373};
2374static const unsigned int i2c2_b_mux[] = {
2375 SDA2_B_MARK, SCL2_B_MARK,
2376};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2377
2378static const unsigned int i2c3_pins[] = {
2379 /* SCL, SDA */
2380 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2381};
2382
2383static const unsigned int i2c3_mux[] = {
2384 SCL3_MARK, SDA3_MARK,
2385};
2386
2387static const unsigned int i2c5_pins[] = {
2388 /* SCL, SDA */
2389 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2390};
2391
2392static const unsigned int i2c5_mux[] = {
2393 SCL5_MARK, SDA5_MARK,
2394};
2395
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2396static const unsigned int i2c6_a_pins[] = {
2397 /* SDA, SCL */
2398 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2399};
2400static const unsigned int i2c6_a_mux[] = {
2401 SDA6_A_MARK, SCL6_A_MARK,
2402};
2403static const unsigned int i2c6_b_pins[] = {
2404 /* SDA, SCL */
2405 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2406};
2407static const unsigned int i2c6_b_mux[] = {
2408 SDA6_B_MARK, SCL6_B_MARK,
2409};
2410static const unsigned int i2c6_c_pins[] = {
2411 /* SDA, SCL */
2412 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2413};
2414static const unsigned int i2c6_c_mux[] = {
2415 SDA6_C_MARK, SCL6_C_MARK,
2416};
2417
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2418/* - INTC-EX ---------------------------------------------------------------- */
2419static const unsigned int intc_ex_irq0_pins[] = {
2420 /* IRQ0 */
2421 RCAR_GP_PIN(2, 0),
2422};
2423static const unsigned int intc_ex_irq0_mux[] = {
2424 IRQ0_MARK,
2425};
2426static const unsigned int intc_ex_irq1_pins[] = {
2427 /* IRQ1 */
2428 RCAR_GP_PIN(2, 1),
2429};
2430static const unsigned int intc_ex_irq1_mux[] = {
2431 IRQ1_MARK,
2432};
2433static const unsigned int intc_ex_irq2_pins[] = {
2434 /* IRQ2 */
2435 RCAR_GP_PIN(2, 2),
2436};
2437static const unsigned int intc_ex_irq2_mux[] = {
2438 IRQ2_MARK,
2439};
2440static const unsigned int intc_ex_irq3_pins[] = {
2441 /* IRQ3 */
2442 RCAR_GP_PIN(2, 3),
2443};
2444static const unsigned int intc_ex_irq3_mux[] = {
2445 IRQ3_MARK,
2446};
2447static const unsigned int intc_ex_irq4_pins[] = {
2448 /* IRQ4 */
2449 RCAR_GP_PIN(2, 4),
2450};
2451static const unsigned int intc_ex_irq4_mux[] = {
2452 IRQ4_MARK,
2453};
2454static const unsigned int intc_ex_irq5_pins[] = {
2455 /* IRQ5 */
2456 RCAR_GP_PIN(2, 5),
2457};
2458static const unsigned int intc_ex_irq5_mux[] = {
2459 IRQ5_MARK,
2460};
2461
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]2462#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
2463/* - MLB+ ------------------------------------------------------------------- */
2464static const unsigned int mlb_3pin_pins[] = {
2465 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2466};
2467static const unsigned int mlb_3pin_mux[] = {
2468 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2469};
2470#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
2471
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2472/* - MSIOF0 ----------------------------------------------------------------- */
2473static const unsigned int msiof0_clk_pins[] = {
2474 /* SCK */
2475 RCAR_GP_PIN(5, 17),
2476};
2477static const unsigned int msiof0_clk_mux[] = {
2478 MSIOF0_SCK_MARK,
2479};
2480static const unsigned int msiof0_sync_pins[] = {
2481 /* SYNC */
2482 RCAR_GP_PIN(5, 18),
2483};
2484static const unsigned int msiof0_sync_mux[] = {
2485 MSIOF0_SYNC_MARK,
2486};
2487static const unsigned int msiof0_ss1_pins[] = {
2488 /* SS1 */
2489 RCAR_GP_PIN(5, 19),
2490};
2491static const unsigned int msiof0_ss1_mux[] = {
2492 MSIOF0_SS1_MARK,
2493};
2494static const unsigned int msiof0_ss2_pins[] = {
2495 /* SS2 */
2496 RCAR_GP_PIN(5, 21),
2497};
2498static const unsigned int msiof0_ss2_mux[] = {
2499 MSIOF0_SS2_MARK,
2500};
2501static const unsigned int msiof0_txd_pins[] = {
2502 /* TXD */
2503 RCAR_GP_PIN(5, 20),
2504};
2505static const unsigned int msiof0_txd_mux[] = {
2506 MSIOF0_TXD_MARK,
2507};
2508static const unsigned int msiof0_rxd_pins[] = {
2509 /* RXD */
2510 RCAR_GP_PIN(5, 22),
2511};
2512static const unsigned int msiof0_rxd_mux[] = {
2513 MSIOF0_RXD_MARK,
2514};
2515/* - MSIOF1 ----------------------------------------------------------------- */
2516static const unsigned int msiof1_clk_a_pins[] = {
2517 /* SCK */
2518 RCAR_GP_PIN(6, 8),
2519};
2520static const unsigned int msiof1_clk_a_mux[] = {
2521 MSIOF1_SCK_A_MARK,
2522};
2523static const unsigned int msiof1_sync_a_pins[] = {
2524 /* SYNC */
2525 RCAR_GP_PIN(6, 9),
2526};
2527static const unsigned int msiof1_sync_a_mux[] = {
2528 MSIOF1_SYNC_A_MARK,
2529};
2530static const unsigned int msiof1_ss1_a_pins[] = {
2531 /* SS1 */
2532 RCAR_GP_PIN(6, 5),
2533};
2534static const unsigned int msiof1_ss1_a_mux[] = {
2535 MSIOF1_SS1_A_MARK,
2536};
2537static const unsigned int msiof1_ss2_a_pins[] = {
2538 /* SS2 */
2539 RCAR_GP_PIN(6, 6),
2540};
2541static const unsigned int msiof1_ss2_a_mux[] = {
2542 MSIOF1_SS2_A_MARK,
2543};
2544static const unsigned int msiof1_txd_a_pins[] = {
2545 /* TXD */
2546 RCAR_GP_PIN(6, 7),
2547};
2548static const unsigned int msiof1_txd_a_mux[] = {
2549 MSIOF1_TXD_A_MARK,
2550};
2551static const unsigned int msiof1_rxd_a_pins[] = {
2552 /* RXD */
2553 RCAR_GP_PIN(6, 10),
2554};
2555static const unsigned int msiof1_rxd_a_mux[] = {
2556 MSIOF1_RXD_A_MARK,
2557};
2558static const unsigned int msiof1_clk_b_pins[] = {
2559 /* SCK */
2560 RCAR_GP_PIN(5, 9),
2561};
2562static const unsigned int msiof1_clk_b_mux[] = {
2563 MSIOF1_SCK_B_MARK,
2564};
2565static const unsigned int msiof1_sync_b_pins[] = {
2566 /* SYNC */
2567 RCAR_GP_PIN(5, 3),
2568};
2569static const unsigned int msiof1_sync_b_mux[] = {
2570 MSIOF1_SYNC_B_MARK,
2571};
2572static const unsigned int msiof1_ss1_b_pins[] = {
2573 /* SS1 */
2574 RCAR_GP_PIN(5, 4),
2575};
2576static const unsigned int msiof1_ss1_b_mux[] = {
2577 MSIOF1_SS1_B_MARK,
2578};
2579static const unsigned int msiof1_ss2_b_pins[] = {
2580 /* SS2 */
2581 RCAR_GP_PIN(5, 0),
2582};
2583static const unsigned int msiof1_ss2_b_mux[] = {
2584 MSIOF1_SS2_B_MARK,
2585};
2586static const unsigned int msiof1_txd_b_pins[] = {
2587 /* TXD */
2588 RCAR_GP_PIN(5, 8),
2589};
2590static const unsigned int msiof1_txd_b_mux[] = {
2591 MSIOF1_TXD_B_MARK,
2592};
2593static const unsigned int msiof1_rxd_b_pins[] = {
2594 /* RXD */
2595 RCAR_GP_PIN(5, 7),
2596};
2597static const unsigned int msiof1_rxd_b_mux[] = {
2598 MSIOF1_RXD_B_MARK,
2599};
2600static const unsigned int msiof1_clk_c_pins[] = {
2601 /* SCK */
2602 RCAR_GP_PIN(6, 17),
2603};
2604static const unsigned int msiof1_clk_c_mux[] = {
2605 MSIOF1_SCK_C_MARK,
2606};
2607static const unsigned int msiof1_sync_c_pins[] = {
2608 /* SYNC */
2609 RCAR_GP_PIN(6, 18),
2610};
2611static const unsigned int msiof1_sync_c_mux[] = {
2612 MSIOF1_SYNC_C_MARK,
2613};
2614static const unsigned int msiof1_ss1_c_pins[] = {
2615 /* SS1 */
2616 RCAR_GP_PIN(6, 21),
2617};
2618static const unsigned int msiof1_ss1_c_mux[] = {
2619 MSIOF1_SS1_C_MARK,
2620};
2621static const unsigned int msiof1_ss2_c_pins[] = {
2622 /* SS2 */
2623 RCAR_GP_PIN(6, 27),
2624};
2625static const unsigned int msiof1_ss2_c_mux[] = {
2626 MSIOF1_SS2_C_MARK,
2627};
2628static const unsigned int msiof1_txd_c_pins[] = {
2629 /* TXD */
2630 RCAR_GP_PIN(6, 20),
2631};
2632static const unsigned int msiof1_txd_c_mux[] = {
2633 MSIOF1_TXD_C_MARK,
2634};
2635static const unsigned int msiof1_rxd_c_pins[] = {
2636 /* RXD */
2637 RCAR_GP_PIN(6, 19),
2638};
2639static const unsigned int msiof1_rxd_c_mux[] = {
2640 MSIOF1_RXD_C_MARK,
2641};
2642static const unsigned int msiof1_clk_d_pins[] = {
2643 /* SCK */
2644 RCAR_GP_PIN(5, 12),
2645};
2646static const unsigned int msiof1_clk_d_mux[] = {
2647 MSIOF1_SCK_D_MARK,
2648};
2649static const unsigned int msiof1_sync_d_pins[] = {
2650 /* SYNC */
2651 RCAR_GP_PIN(5, 15),
2652};
2653static const unsigned int msiof1_sync_d_mux[] = {
2654 MSIOF1_SYNC_D_MARK,
2655};
2656static const unsigned int msiof1_ss1_d_pins[] = {
2657 /* SS1 */
2658 RCAR_GP_PIN(5, 16),
2659};
2660static const unsigned int msiof1_ss1_d_mux[] = {
2661 MSIOF1_SS1_D_MARK,
2662};
2663static const unsigned int msiof1_ss2_d_pins[] = {
2664 /* SS2 */
2665 RCAR_GP_PIN(5, 21),
2666};
2667static const unsigned int msiof1_ss2_d_mux[] = {
2668 MSIOF1_SS2_D_MARK,
2669};
2670static const unsigned int msiof1_txd_d_pins[] = {
2671 /* TXD */
2672 RCAR_GP_PIN(5, 14),
2673};
2674static const unsigned int msiof1_txd_d_mux[] = {
2675 MSIOF1_TXD_D_MARK,
2676};
2677static const unsigned int msiof1_rxd_d_pins[] = {
2678 /* RXD */
2679 RCAR_GP_PIN(5, 13),
2680};
2681static const unsigned int msiof1_rxd_d_mux[] = {
2682 MSIOF1_RXD_D_MARK,
2683};
2684static const unsigned int msiof1_clk_e_pins[] = {
2685 /* SCK */
2686 RCAR_GP_PIN(3, 0),
2687};
2688static const unsigned int msiof1_clk_e_mux[] = {
2689 MSIOF1_SCK_E_MARK,
2690};
2691static const unsigned int msiof1_sync_e_pins[] = {
2692 /* SYNC */
2693 RCAR_GP_PIN(3, 1),
2694};
2695static const unsigned int msiof1_sync_e_mux[] = {
2696 MSIOF1_SYNC_E_MARK,
2697};
2698static const unsigned int msiof1_ss1_e_pins[] = {
2699 /* SS1 */
2700 RCAR_GP_PIN(3, 4),
2701};
2702static const unsigned int msiof1_ss1_e_mux[] = {
2703 MSIOF1_SS1_E_MARK,
2704};
2705static const unsigned int msiof1_ss2_e_pins[] = {
2706 /* SS2 */
2707 RCAR_GP_PIN(3, 5),
2708};
2709static const unsigned int msiof1_ss2_e_mux[] = {
2710 MSIOF1_SS2_E_MARK,
2711};
2712static const unsigned int msiof1_txd_e_pins[] = {
2713 /* TXD */
2714 RCAR_GP_PIN(3, 3),
2715};
2716static const unsigned int msiof1_txd_e_mux[] = {
2717 MSIOF1_TXD_E_MARK,
2718};
2719static const unsigned int msiof1_rxd_e_pins[] = {
2720 /* RXD */
2721 RCAR_GP_PIN(3, 2),
2722};
2723static const unsigned int msiof1_rxd_e_mux[] = {
2724 MSIOF1_RXD_E_MARK,
2725};
2726static const unsigned int msiof1_clk_f_pins[] = {
2727 /* SCK */
2728 RCAR_GP_PIN(5, 23),
2729};
2730static const unsigned int msiof1_clk_f_mux[] = {
2731 MSIOF1_SCK_F_MARK,
2732};
2733static const unsigned int msiof1_sync_f_pins[] = {
2734 /* SYNC */
2735 RCAR_GP_PIN(5, 24),
2736};
2737static const unsigned int msiof1_sync_f_mux[] = {
2738 MSIOF1_SYNC_F_MARK,
2739};
2740static const unsigned int msiof1_ss1_f_pins[] = {
2741 /* SS1 */
2742 RCAR_GP_PIN(6, 1),
2743};
2744static const unsigned int msiof1_ss1_f_mux[] = {
2745 MSIOF1_SS1_F_MARK,
2746};
2747static const unsigned int msiof1_ss2_f_pins[] = {
2748 /* SS2 */
2749 RCAR_GP_PIN(6, 2),
2750};
2751static const unsigned int msiof1_ss2_f_mux[] = {
2752 MSIOF1_SS2_F_MARK,
2753};
2754static const unsigned int msiof1_txd_f_pins[] = {
2755 /* TXD */
2756 RCAR_GP_PIN(6, 0),
2757};
2758static const unsigned int msiof1_txd_f_mux[] = {
2759 MSIOF1_TXD_F_MARK,
2760};
2761static const unsigned int msiof1_rxd_f_pins[] = {
2762 /* RXD */
2763 RCAR_GP_PIN(5, 25),
2764};
2765static const unsigned int msiof1_rxd_f_mux[] = {
2766 MSIOF1_RXD_F_MARK,
2767};
2768static const unsigned int msiof1_clk_g_pins[] = {
2769 /* SCK */
2770 RCAR_GP_PIN(3, 6),
2771};
2772static const unsigned int msiof1_clk_g_mux[] = {
2773 MSIOF1_SCK_G_MARK,
2774};
2775static const unsigned int msiof1_sync_g_pins[] = {
2776 /* SYNC */
2777 RCAR_GP_PIN(3, 7),
2778};
2779static const unsigned int msiof1_sync_g_mux[] = {
2780 MSIOF1_SYNC_G_MARK,
2781};
2782static const unsigned int msiof1_ss1_g_pins[] = {
2783 /* SS1 */
2784 RCAR_GP_PIN(3, 10),
2785};
2786static const unsigned int msiof1_ss1_g_mux[] = {
2787 MSIOF1_SS1_G_MARK,
2788};
2789static const unsigned int msiof1_ss2_g_pins[] = {
2790 /* SS2 */
2791 RCAR_GP_PIN(3, 11),
2792};
2793static const unsigned int msiof1_ss2_g_mux[] = {
2794 MSIOF1_SS2_G_MARK,
2795};
2796static const unsigned int msiof1_txd_g_pins[] = {
2797 /* TXD */
2798 RCAR_GP_PIN(3, 9),
2799};
2800static const unsigned int msiof1_txd_g_mux[] = {
2801 MSIOF1_TXD_G_MARK,
2802};
2803static const unsigned int msiof1_rxd_g_pins[] = {
2804 /* RXD */
2805 RCAR_GP_PIN(3, 8),
2806};
2807static const unsigned int msiof1_rxd_g_mux[] = {
2808 MSIOF1_RXD_G_MARK,
2809};
2810/* - MSIOF2 ----------------------------------------------------------------- */
2811static const unsigned int msiof2_clk_a_pins[] = {
2812 /* SCK */
2813 RCAR_GP_PIN(1, 9),
2814};
2815static const unsigned int msiof2_clk_a_mux[] = {
2816 MSIOF2_SCK_A_MARK,
2817};
2818static const unsigned int msiof2_sync_a_pins[] = {
2819 /* SYNC */
2820 RCAR_GP_PIN(1, 8),
2821};
2822static const unsigned int msiof2_sync_a_mux[] = {
2823 MSIOF2_SYNC_A_MARK,
2824};
2825static const unsigned int msiof2_ss1_a_pins[] = {
2826 /* SS1 */
2827 RCAR_GP_PIN(1, 6),
2828};
2829static const unsigned int msiof2_ss1_a_mux[] = {
2830 MSIOF2_SS1_A_MARK,
2831};
2832static const unsigned int msiof2_ss2_a_pins[] = {
2833 /* SS2 */
2834 RCAR_GP_PIN(1, 7),
2835};
2836static const unsigned int msiof2_ss2_a_mux[] = {
2837 MSIOF2_SS2_A_MARK,
2838};
2839static const unsigned int msiof2_txd_a_pins[] = {
2840 /* TXD */
2841 RCAR_GP_PIN(1, 11),
2842};
2843static const unsigned int msiof2_txd_a_mux[] = {
2844 MSIOF2_TXD_A_MARK,
2845};
2846static const unsigned int msiof2_rxd_a_pins[] = {
2847 /* RXD */
2848 RCAR_GP_PIN(1, 10),
2849};
2850static const unsigned int msiof2_rxd_a_mux[] = {
2851 MSIOF2_RXD_A_MARK,
2852};
2853static const unsigned int msiof2_clk_b_pins[] = {
2854 /* SCK */
2855 RCAR_GP_PIN(0, 4),
2856};
2857static const unsigned int msiof2_clk_b_mux[] = {
2858 MSIOF2_SCK_B_MARK,
2859};
2860static const unsigned int msiof2_sync_b_pins[] = {
2861 /* SYNC */
2862 RCAR_GP_PIN(0, 5),
2863};
2864static const unsigned int msiof2_sync_b_mux[] = {
2865 MSIOF2_SYNC_B_MARK,
2866};
2867static const unsigned int msiof2_ss1_b_pins[] = {
2868 /* SS1 */
2869 RCAR_GP_PIN(0, 0),
2870};
2871static const unsigned int msiof2_ss1_b_mux[] = {
2872 MSIOF2_SS1_B_MARK,
2873};
2874static const unsigned int msiof2_ss2_b_pins[] = {
2875 /* SS2 */
2876 RCAR_GP_PIN(0, 1),
2877};
2878static const unsigned int msiof2_ss2_b_mux[] = {
2879 MSIOF2_SS2_B_MARK,
2880};
2881static const unsigned int msiof2_txd_b_pins[] = {
2882 /* TXD */
2883 RCAR_GP_PIN(0, 7),
2884};
2885static const unsigned int msiof2_txd_b_mux[] = {
2886 MSIOF2_TXD_B_MARK,
2887};
2888static const unsigned int msiof2_rxd_b_pins[] = {
2889 /* RXD */
2890 RCAR_GP_PIN(0, 6),
2891};
2892static const unsigned int msiof2_rxd_b_mux[] = {
2893 MSIOF2_RXD_B_MARK,
2894};
2895static const unsigned int msiof2_clk_c_pins[] = {
2896 /* SCK */
2897 RCAR_GP_PIN(2, 12),
2898};
2899static const unsigned int msiof2_clk_c_mux[] = {
2900 MSIOF2_SCK_C_MARK,
2901};
2902static const unsigned int msiof2_sync_c_pins[] = {
2903 /* SYNC */
2904 RCAR_GP_PIN(2, 11),
2905};
2906static const unsigned int msiof2_sync_c_mux[] = {
2907 MSIOF2_SYNC_C_MARK,
2908};
2909static const unsigned int msiof2_ss1_c_pins[] = {
2910 /* SS1 */
2911 RCAR_GP_PIN(2, 10),
2912};
2913static const unsigned int msiof2_ss1_c_mux[] = {
2914 MSIOF2_SS1_C_MARK,
2915};
2916static const unsigned int msiof2_ss2_c_pins[] = {
2917 /* SS2 */
2918 RCAR_GP_PIN(2, 9),
2919};
2920static const unsigned int msiof2_ss2_c_mux[] = {
2921 MSIOF2_SS2_C_MARK,
2922};
2923static const unsigned int msiof2_txd_c_pins[] = {
2924 /* TXD */
2925 RCAR_GP_PIN(2, 14),
2926};
2927static const unsigned int msiof2_txd_c_mux[] = {
2928 MSIOF2_TXD_C_MARK,
2929};
2930static const unsigned int msiof2_rxd_c_pins[] = {
2931 /* RXD */
2932 RCAR_GP_PIN(2, 13),
2933};
2934static const unsigned int msiof2_rxd_c_mux[] = {
2935 MSIOF2_RXD_C_MARK,
2936};
2937static const unsigned int msiof2_clk_d_pins[] = {
2938 /* SCK */
2939 RCAR_GP_PIN(0, 8),
2940};
2941static const unsigned int msiof2_clk_d_mux[] = {
2942 MSIOF2_SCK_D_MARK,
2943};
2944static const unsigned int msiof2_sync_d_pins[] = {
2945 /* SYNC */
2946 RCAR_GP_PIN(0, 9),
2947};
2948static const unsigned int msiof2_sync_d_mux[] = {
2949 MSIOF2_SYNC_D_MARK,
2950};
2951static const unsigned int msiof2_ss1_d_pins[] = {
2952 /* SS1 */
2953 RCAR_GP_PIN(0, 12),
2954};
2955static const unsigned int msiof2_ss1_d_mux[] = {
2956 MSIOF2_SS1_D_MARK,
2957};
2958static const unsigned int msiof2_ss2_d_pins[] = {
2959 /* SS2 */
2960 RCAR_GP_PIN(0, 13),
2961};
2962static const unsigned int msiof2_ss2_d_mux[] = {
2963 MSIOF2_SS2_D_MARK,
2964};
2965static const unsigned int msiof2_txd_d_pins[] = {
2966 /* TXD */
2967 RCAR_GP_PIN(0, 11),
2968};
2969static const unsigned int msiof2_txd_d_mux[] = {
2970 MSIOF2_TXD_D_MARK,
2971};
2972static const unsigned int msiof2_rxd_d_pins[] = {
2973 /* RXD */
2974 RCAR_GP_PIN(0, 10),
2975};
2976static const unsigned int msiof2_rxd_d_mux[] = {
2977 MSIOF2_RXD_D_MARK,
2978};
2979/* - MSIOF3 ----------------------------------------------------------------- */
2980static const unsigned int msiof3_clk_a_pins[] = {
2981 /* SCK */
2982 RCAR_GP_PIN(0, 0),
2983};
2984static const unsigned int msiof3_clk_a_mux[] = {
2985 MSIOF3_SCK_A_MARK,
2986};
2987static const unsigned int msiof3_sync_a_pins[] = {
2988 /* SYNC */
2989 RCAR_GP_PIN(0, 1),
2990};
2991static const unsigned int msiof3_sync_a_mux[] = {
2992 MSIOF3_SYNC_A_MARK,
2993};
2994static const unsigned int msiof3_ss1_a_pins[] = {
2995 /* SS1 */
2996 RCAR_GP_PIN(0, 14),
2997};
2998static const unsigned int msiof3_ss1_a_mux[] = {
2999 MSIOF3_SS1_A_MARK,
3000};
3001static const unsigned int msiof3_ss2_a_pins[] = {
3002 /* SS2 */
3003 RCAR_GP_PIN(0, 15),
3004};
3005static const unsigned int msiof3_ss2_a_mux[] = {
3006 MSIOF3_SS2_A_MARK,
3007};
3008static const unsigned int msiof3_txd_a_pins[] = {
3009 /* TXD */
3010 RCAR_GP_PIN(0, 3),
3011};
3012static const unsigned int msiof3_txd_a_mux[] = {
3013 MSIOF3_TXD_A_MARK,
3014};
3015static const unsigned int msiof3_rxd_a_pins[] = {
3016 /* RXD */
3017 RCAR_GP_PIN(0, 2),
3018};
3019static const unsigned int msiof3_rxd_a_mux[] = {
3020 MSIOF3_RXD_A_MARK,
3021};
3022static const unsigned int msiof3_clk_b_pins[] = {
3023 /* SCK */
3024 RCAR_GP_PIN(1, 2),
3025};
3026static const unsigned int msiof3_clk_b_mux[] = {
3027 MSIOF3_SCK_B_MARK,
3028};
3029static const unsigned int msiof3_sync_b_pins[] = {
3030 /* SYNC */
3031 RCAR_GP_PIN(1, 0),
3032};
3033static const unsigned int msiof3_sync_b_mux[] = {
3034 MSIOF3_SYNC_B_MARK,
3035};
3036static const unsigned int msiof3_ss1_b_pins[] = {
3037 /* SS1 */
3038 RCAR_GP_PIN(1, 4),
3039};
3040static const unsigned int msiof3_ss1_b_mux[] = {
3041 MSIOF3_SS1_B_MARK,
3042};
3043static const unsigned int msiof3_ss2_b_pins[] = {
3044 /* SS2 */
3045 RCAR_GP_PIN(1, 5),
3046};
3047static const unsigned int msiof3_ss2_b_mux[] = {
3048 MSIOF3_SS2_B_MARK,
3049};
3050static const unsigned int msiof3_txd_b_pins[] = {
3051 /* TXD */
3052 RCAR_GP_PIN(1, 1),
3053};
3054static const unsigned int msiof3_txd_b_mux[] = {
3055 MSIOF3_TXD_B_MARK,
3056};
3057static const unsigned int msiof3_rxd_b_pins[] = {
3058 /* RXD */
3059 RCAR_GP_PIN(1, 3),
3060};
3061static const unsigned int msiof3_rxd_b_mux[] = {
3062 MSIOF3_RXD_B_MARK,
3063};
3064static const unsigned int msiof3_clk_c_pins[] = {
3065 /* SCK */
3066 RCAR_GP_PIN(1, 12),
3067};
3068static const unsigned int msiof3_clk_c_mux[] = {
3069 MSIOF3_SCK_C_MARK,
3070};
3071static const unsigned int msiof3_sync_c_pins[] = {
3072 /* SYNC */
3073 RCAR_GP_PIN(1, 13),
3074};
3075static const unsigned int msiof3_sync_c_mux[] = {
3076 MSIOF3_SYNC_C_MARK,
3077};
3078static const unsigned int msiof3_txd_c_pins[] = {
3079 /* TXD */
3080 RCAR_GP_PIN(1, 15),
3081};
3082static const unsigned int msiof3_txd_c_mux[] = {
3083 MSIOF3_TXD_C_MARK,
3084};
3085static const unsigned int msiof3_rxd_c_pins[] = {
3086 /* RXD */
3087 RCAR_GP_PIN(1, 14),
3088};
3089static const unsigned int msiof3_rxd_c_mux[] = {
3090 MSIOF3_RXD_C_MARK,
3091};
3092static const unsigned int msiof3_clk_d_pins[] = {
3093 /* SCK */
3094 RCAR_GP_PIN(1, 22),
3095};
3096static const unsigned int msiof3_clk_d_mux[] = {
3097 MSIOF3_SCK_D_MARK,
3098};
3099static const unsigned int msiof3_sync_d_pins[] = {
3100 /* SYNC */
3101 RCAR_GP_PIN(1, 23),
3102};
3103static const unsigned int msiof3_sync_d_mux[] = {
3104 MSIOF3_SYNC_D_MARK,
3105};
3106static const unsigned int msiof3_ss1_d_pins[] = {
3107 /* SS1 */
3108 RCAR_GP_PIN(1, 26),
3109};
3110static const unsigned int msiof3_ss1_d_mux[] = {
3111 MSIOF3_SS1_D_MARK,
3112};
3113static const unsigned int msiof3_txd_d_pins[] = {
3114 /* TXD */
3115 RCAR_GP_PIN(1, 25),
3116};
3117static const unsigned int msiof3_txd_d_mux[] = {
3118 MSIOF3_TXD_D_MARK,
3119};
3120static const unsigned int msiof3_rxd_d_pins[] = {
3121 /* RXD */
3122 RCAR_GP_PIN(1, 24),
3123};
3124static const unsigned int msiof3_rxd_d_mux[] = {
3125 MSIOF3_RXD_D_MARK,
3126};
3127
3128static const unsigned int msiof3_clk_e_pins[] = {
3129 /* SCK */
3130 RCAR_GP_PIN(2, 3),
3131};
3132static const unsigned int msiof3_clk_e_mux[] = {
3133 MSIOF3_SCK_E_MARK,
3134};
3135static const unsigned int msiof3_sync_e_pins[] = {
3136 /* SYNC */
3137 RCAR_GP_PIN(2, 2),
3138};
3139static const unsigned int msiof3_sync_e_mux[] = {
3140 MSIOF3_SYNC_E_MARK,
3141};
3142static const unsigned int msiof3_ss1_e_pins[] = {
3143 /* SS1 */
3144 RCAR_GP_PIN(2, 1),
3145};
3146static const unsigned int msiof3_ss1_e_mux[] = {
3147 MSIOF3_SS1_E_MARK,
3148};
3149static const unsigned int msiof3_ss2_e_pins[] = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]3150 /* SS2 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3151 RCAR_GP_PIN(2, 0),
3152};
3153static const unsigned int msiof3_ss2_e_mux[] = {
3154 MSIOF3_SS2_E_MARK,
3155};
3156static const unsigned int msiof3_txd_e_pins[] = {
3157 /* TXD */
3158 RCAR_GP_PIN(2, 5),
3159};
3160static const unsigned int msiof3_txd_e_mux[] = {
3161 MSIOF3_TXD_E_MARK,
3162};
3163static const unsigned int msiof3_rxd_e_pins[] = {
3164 /* RXD */
3165 RCAR_GP_PIN(2, 4),
3166};
3167static const unsigned int msiof3_rxd_e_mux[] = {
3168 MSIOF3_RXD_E_MARK,
3169};
3170
3171/* - PWM0 --------------------------------------------------------------------*/
3172static const unsigned int pwm0_pins[] = {
3173 /* PWM */
3174 RCAR_GP_PIN(2, 6),
3175};
3176static const unsigned int pwm0_mux[] = {
3177 PWM0_MARK,
3178};
3179/* - PWM1 --------------------------------------------------------------------*/
3180static const unsigned int pwm1_a_pins[] = {
3181 /* PWM */
3182 RCAR_GP_PIN(2, 7),
3183};
3184static const unsigned int pwm1_a_mux[] = {
3185 PWM1_A_MARK,
3186};
3187static const unsigned int pwm1_b_pins[] = {
3188 /* PWM */
3189 RCAR_GP_PIN(1, 8),
3190};
3191static const unsigned int pwm1_b_mux[] = {
3192 PWM1_B_MARK,
3193};
3194/* - PWM2 --------------------------------------------------------------------*/
3195static const unsigned int pwm2_a_pins[] = {
3196 /* PWM */
3197 RCAR_GP_PIN(2, 8),
3198};
3199static const unsigned int pwm2_a_mux[] = {
3200 PWM2_A_MARK,
3201};
3202static const unsigned int pwm2_b_pins[] = {
3203 /* PWM */
3204 RCAR_GP_PIN(1, 11),
3205};
3206static const unsigned int pwm2_b_mux[] = {
3207 PWM2_B_MARK,
3208};
3209/* - PWM3 --------------------------------------------------------------------*/
3210static const unsigned int pwm3_a_pins[] = {
3211 /* PWM */
3212 RCAR_GP_PIN(1, 0),
3213};
3214static const unsigned int pwm3_a_mux[] = {
3215 PWM3_A_MARK,
3216};
3217static const unsigned int pwm3_b_pins[] = {
3218 /* PWM */
3219 RCAR_GP_PIN(2, 2),
3220};
3221static const unsigned int pwm3_b_mux[] = {
3222 PWM3_B_MARK,
3223};
3224/* - PWM4 --------------------------------------------------------------------*/
3225static const unsigned int pwm4_a_pins[] = {
3226 /* PWM */
3227 RCAR_GP_PIN(1, 1),
3228};
3229static const unsigned int pwm4_a_mux[] = {
3230 PWM4_A_MARK,
3231};
3232static const unsigned int pwm4_b_pins[] = {
3233 /* PWM */
3234 RCAR_GP_PIN(2, 3),
3235};
3236static const unsigned int pwm4_b_mux[] = {
3237 PWM4_B_MARK,
3238};
3239/* - PWM5 --------------------------------------------------------------------*/
3240static const unsigned int pwm5_a_pins[] = {
3241 /* PWM */
3242 RCAR_GP_PIN(1, 2),
3243};
3244static const unsigned int pwm5_a_mux[] = {
3245 PWM5_A_MARK,
3246};
3247static const unsigned int pwm5_b_pins[] = {
3248 /* PWM */
3249 RCAR_GP_PIN(2, 4),
3250};
3251static const unsigned int pwm5_b_mux[] = {
3252 PWM5_B_MARK,
3253};
3254/* - PWM6 --------------------------------------------------------------------*/
3255static const unsigned int pwm6_a_pins[] = {
3256 /* PWM */
3257 RCAR_GP_PIN(1, 3),
3258};
3259static const unsigned int pwm6_a_mux[] = {
3260 PWM6_A_MARK,
3261};
3262static const unsigned int pwm6_b_pins[] = {
3263 /* PWM */
3264 RCAR_GP_PIN(2, 5),
3265};
3266static const unsigned int pwm6_b_mux[] = {
3267 PWM6_B_MARK,
3268};
3269
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3270/* - QSPI0 ------------------------------------------------------------------ */
3271static const unsigned int qspi0_ctrl_pins[] = {
3272 /* QSPI0_SPCLK, QSPI0_SSL */
3273 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3274};
3275static const unsigned int qspi0_ctrl_mux[] = {
3276 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3277};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3278static const unsigned int qspi0_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3279 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3280 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3281 /* QSPI0_IO2, QSPI0_IO3 */
3282 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3283};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3284static const unsigned int qspi0_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3285 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3286 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3287};
3288/* - QSPI1 ------------------------------------------------------------------ */
3289static const unsigned int qspi1_ctrl_pins[] = {
3290 /* QSPI1_SPCLK, QSPI1_SSL */
3291 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3292};
3293static const unsigned int qspi1_ctrl_mux[] = {
3294 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3295};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3296static const unsigned int qspi1_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3297 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3298 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3299 /* QSPI1_IO2, QSPI1_IO3 */
3300 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3301};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3302static const unsigned int qspi1_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3303 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3304 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3305};
3306
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3307/* - SCIF0 ------------------------------------------------------------------ */
3308static const unsigned int scif0_data_pins[] = {
3309 /* RX, TX */
3310 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3311};
3312static const unsigned int scif0_data_mux[] = {
3313 RX0_MARK, TX0_MARK,
3314};
3315static const unsigned int scif0_clk_pins[] = {
3316 /* SCK */
3317 RCAR_GP_PIN(5, 0),
3318};
3319static const unsigned int scif0_clk_mux[] = {
3320 SCK0_MARK,
3321};
3322static const unsigned int scif0_ctrl_pins[] = {
3323 /* RTS, CTS */
3324 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3325};
3326static const unsigned int scif0_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3327 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3328};
3329/* - SCIF1 ------------------------------------------------------------------ */
3330static const unsigned int scif1_data_a_pins[] = {
3331 /* RX, TX */
3332 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3333};
3334static const unsigned int scif1_data_a_mux[] = {
3335 RX1_A_MARK, TX1_A_MARK,
3336};
3337static const unsigned int scif1_clk_pins[] = {
3338 /* SCK */
3339 RCAR_GP_PIN(6, 21),
3340};
3341static const unsigned int scif1_clk_mux[] = {
3342 SCK1_MARK,
3343};
3344static const unsigned int scif1_ctrl_pins[] = {
3345 /* RTS, CTS */
3346 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3347};
3348static const unsigned int scif1_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3349 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3350};
3351
3352static const unsigned int scif1_data_b_pins[] = {
3353 /* RX, TX */
3354 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3355};
3356static const unsigned int scif1_data_b_mux[] = {
3357 RX1_B_MARK, TX1_B_MARK,
3358};
3359/* - SCIF2 ------------------------------------------------------------------ */
3360static const unsigned int scif2_data_a_pins[] = {
3361 /* RX, TX */
3362 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3363};
3364static const unsigned int scif2_data_a_mux[] = {
3365 RX2_A_MARK, TX2_A_MARK,
3366};
3367static const unsigned int scif2_clk_pins[] = {
3368 /* SCK */
3369 RCAR_GP_PIN(5, 9),
3370};
3371static const unsigned int scif2_clk_mux[] = {
3372 SCK2_MARK,
3373};
3374static const unsigned int scif2_data_b_pins[] = {
3375 /* RX, TX */
3376 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3377};
3378static const unsigned int scif2_data_b_mux[] = {
3379 RX2_B_MARK, TX2_B_MARK,
3380};
3381/* - SCIF3 ------------------------------------------------------------------ */
3382static const unsigned int scif3_data_a_pins[] = {
3383 /* RX, TX */
3384 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3385};
3386static const unsigned int scif3_data_a_mux[] = {
3387 RX3_A_MARK, TX3_A_MARK,
3388};
3389static const unsigned int scif3_clk_pins[] = {
3390 /* SCK */
3391 RCAR_GP_PIN(1, 22),
3392};
3393static const unsigned int scif3_clk_mux[] = {
3394 SCK3_MARK,
3395};
3396static const unsigned int scif3_ctrl_pins[] = {
3397 /* RTS, CTS */
3398 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3399};
3400static const unsigned int scif3_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3401 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3402};
3403static const unsigned int scif3_data_b_pins[] = {
3404 /* RX, TX */
3405 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3406};
3407static const unsigned int scif3_data_b_mux[] = {
3408 RX3_B_MARK, TX3_B_MARK,
3409};
3410/* - SCIF4 ------------------------------------------------------------------ */
3411static const unsigned int scif4_data_a_pins[] = {
3412 /* RX, TX */
3413 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3414};
3415static const unsigned int scif4_data_a_mux[] = {
3416 RX4_A_MARK, TX4_A_MARK,
3417};
3418static const unsigned int scif4_clk_a_pins[] = {
3419 /* SCK */
3420 RCAR_GP_PIN(2, 10),
3421};
3422static const unsigned int scif4_clk_a_mux[] = {
3423 SCK4_A_MARK,
3424};
3425static const unsigned int scif4_ctrl_a_pins[] = {
3426 /* RTS, CTS */
3427 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3428};
3429static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3430 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3431};
3432static const unsigned int scif4_data_b_pins[] = {
3433 /* RX, TX */
3434 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3435};
3436static const unsigned int scif4_data_b_mux[] = {
3437 RX4_B_MARK, TX4_B_MARK,
3438};
3439static const unsigned int scif4_clk_b_pins[] = {
3440 /* SCK */
3441 RCAR_GP_PIN(1, 5),
3442};
3443static const unsigned int scif4_clk_b_mux[] = {
3444 SCK4_B_MARK,
3445};
3446static const unsigned int scif4_ctrl_b_pins[] = {
3447 /* RTS, CTS */
3448 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3449};
3450static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3451 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3452};
3453static const unsigned int scif4_data_c_pins[] = {
3454 /* RX, TX */
3455 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3456};
3457static const unsigned int scif4_data_c_mux[] = {
3458 RX4_C_MARK, TX4_C_MARK,
3459};
3460static const unsigned int scif4_clk_c_pins[] = {
3461 /* SCK */
3462 RCAR_GP_PIN(0, 8),
3463};
3464static const unsigned int scif4_clk_c_mux[] = {
3465 SCK4_C_MARK,
3466};
3467static const unsigned int scif4_ctrl_c_pins[] = {
3468 /* RTS, CTS */
3469 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3470};
3471static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3472 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3473};
3474/* - SCIF5 ------------------------------------------------------------------ */
3475static const unsigned int scif5_data_a_pins[] = {
3476 /* RX, TX */
3477 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3478};
3479static const unsigned int scif5_data_a_mux[] = {
3480 RX5_A_MARK, TX5_A_MARK,
3481};
3482static const unsigned int scif5_clk_a_pins[] = {
3483 /* SCK */
3484 RCAR_GP_PIN(6, 21),
3485};
3486static const unsigned int scif5_clk_a_mux[] = {
3487 SCK5_A_MARK,
3488};
3489
3490static const unsigned int scif5_data_b_pins[] = {
3491 /* RX, TX */
3492 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3493};
3494static const unsigned int scif5_data_b_mux[] = {
3495 RX5_B_MARK, TX5_B_MARK,
3496};
3497static const unsigned int scif5_clk_b_pins[] = {
3498 /* SCK */
3499 RCAR_GP_PIN(5, 0),
3500};
3501static const unsigned int scif5_clk_b_mux[] = {
3502 SCK5_B_MARK,
3503};
3504
3505/* - SCIF Clock ------------------------------------------------------------- */
3506static const unsigned int scif_clk_a_pins[] = {
3507 /* SCIF_CLK */
3508 RCAR_GP_PIN(6, 23),
3509};
3510static const unsigned int scif_clk_a_mux[] = {
3511 SCIF_CLK_A_MARK,
3512};
3513static const unsigned int scif_clk_b_pins[] = {
3514 /* SCIF_CLK */
3515 RCAR_GP_PIN(5, 9),
3516};
3517static const unsigned int scif_clk_b_mux[] = {
3518 SCIF_CLK_B_MARK,
3519};
3520
3521/* - SDHI0 ------------------------------------------------------------------ */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3522static const unsigned int sdhi0_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3523 /* D[0:3] */
3524 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3525 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3526};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3527static const unsigned int sdhi0_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3528 SD0_DAT0_MARK, SD0_DAT1_MARK,
3529 SD0_DAT2_MARK, SD0_DAT3_MARK,
3530};
3531static const unsigned int sdhi0_ctrl_pins[] = {
3532 /* CLK, CMD */
3533 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3534};
3535static const unsigned int sdhi0_ctrl_mux[] = {
3536 SD0_CLK_MARK, SD0_CMD_MARK,
3537};
3538static const unsigned int sdhi0_cd_pins[] = {
3539 /* CD */
3540 RCAR_GP_PIN(3, 12),
3541};
3542static const unsigned int sdhi0_cd_mux[] = {
3543 SD0_CD_MARK,
3544};
3545static const unsigned int sdhi0_wp_pins[] = {
3546 /* WP */
3547 RCAR_GP_PIN(3, 13),
3548};
3549static const unsigned int sdhi0_wp_mux[] = {
3550 SD0_WP_MARK,
3551};
3552/* - SDHI1 ------------------------------------------------------------------ */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3553static const unsigned int sdhi1_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3554 /* D[0:3] */
3555 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3556 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3557};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3558static const unsigned int sdhi1_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3559 SD1_DAT0_MARK, SD1_DAT1_MARK,
3560 SD1_DAT2_MARK, SD1_DAT3_MARK,
3561};
3562static const unsigned int sdhi1_ctrl_pins[] = {
3563 /* CLK, CMD */
3564 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3565};
3566static const unsigned int sdhi1_ctrl_mux[] = {
3567 SD1_CLK_MARK, SD1_CMD_MARK,
3568};
3569static const unsigned int sdhi1_cd_pins[] = {
3570 /* CD */
3571 RCAR_GP_PIN(3, 14),
3572};
3573static const unsigned int sdhi1_cd_mux[] = {
3574 SD1_CD_MARK,
3575};
3576static const unsigned int sdhi1_wp_pins[] = {
3577 /* WP */
3578 RCAR_GP_PIN(3, 15),
3579};
3580static const unsigned int sdhi1_wp_mux[] = {
3581 SD1_WP_MARK,
3582};
3583/* - SDHI2 ------------------------------------------------------------------ */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3584static const unsigned int sdhi2_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3585 /* D[0:7] */
3586 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3587 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3588 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3589 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3590};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3591static const unsigned int sdhi2_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3592 SD2_DAT0_MARK, SD2_DAT1_MARK,
3593 SD2_DAT2_MARK, SD2_DAT3_MARK,
3594 SD2_DAT4_MARK, SD2_DAT5_MARK,
3595 SD2_DAT6_MARK, SD2_DAT7_MARK,
3596};
3597static const unsigned int sdhi2_ctrl_pins[] = {
3598 /* CLK, CMD */
3599 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3600};
3601static const unsigned int sdhi2_ctrl_mux[] = {
3602 SD2_CLK_MARK, SD2_CMD_MARK,
3603};
3604static const unsigned int sdhi2_cd_a_pins[] = {
3605 /* CD */
3606 RCAR_GP_PIN(4, 13),
3607};
3608static const unsigned int sdhi2_cd_a_mux[] = {
3609 SD2_CD_A_MARK,
3610};
3611static const unsigned int sdhi2_cd_b_pins[] = {
3612 /* CD */
3613 RCAR_GP_PIN(5, 10),
3614};
3615static const unsigned int sdhi2_cd_b_mux[] = {
3616 SD2_CD_B_MARK,
3617};
3618static const unsigned int sdhi2_wp_a_pins[] = {
3619 /* WP */
3620 RCAR_GP_PIN(4, 14),
3621};
3622static const unsigned int sdhi2_wp_a_mux[] = {
3623 SD2_WP_A_MARK,
3624};
3625static const unsigned int sdhi2_wp_b_pins[] = {
3626 /* WP */
3627 RCAR_GP_PIN(5, 11),
3628};
3629static const unsigned int sdhi2_wp_b_mux[] = {
3630 SD2_WP_B_MARK,
3631};
3632static const unsigned int sdhi2_ds_pins[] = {
3633 /* DS */
3634 RCAR_GP_PIN(4, 6),
3635};
3636static const unsigned int sdhi2_ds_mux[] = {
3637 SD2_DS_MARK,
3638};
3639/* - SDHI3 ------------------------------------------------------------------ */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3640static const unsigned int sdhi3_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3641 /* D[0:7] */
3642 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3643 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3644 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3645 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3646};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3647static const unsigned int sdhi3_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3648 SD3_DAT0_MARK, SD3_DAT1_MARK,
3649 SD3_DAT2_MARK, SD3_DAT3_MARK,
3650 SD3_DAT4_MARK, SD3_DAT5_MARK,
3651 SD3_DAT6_MARK, SD3_DAT7_MARK,
3652};
3653static const unsigned int sdhi3_ctrl_pins[] = {
3654 /* CLK, CMD */
3655 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3656};
3657static const unsigned int sdhi3_ctrl_mux[] = {
3658 SD3_CLK_MARK, SD3_CMD_MARK,
3659};
3660static const unsigned int sdhi3_cd_pins[] = {
3661 /* CD */
3662 RCAR_GP_PIN(4, 15),
3663};
3664static const unsigned int sdhi3_cd_mux[] = {
3665 SD3_CD_MARK,
3666};
3667static const unsigned int sdhi3_wp_pins[] = {
3668 /* WP */
3669 RCAR_GP_PIN(4, 16),
3670};
3671static const unsigned int sdhi3_wp_mux[] = {
3672 SD3_WP_MARK,
3673};
3674static const unsigned int sdhi3_ds_pins[] = {
3675 /* DS */
3676 RCAR_GP_PIN(4, 17),
3677};
3678static const unsigned int sdhi3_ds_mux[] = {
3679 SD3_DS_MARK,
3680};
3681
3682/* - SSI -------------------------------------------------------------------- */
3683static const unsigned int ssi0_data_pins[] = {
3684 /* SDATA */
3685 RCAR_GP_PIN(6, 2),
3686};
3687static const unsigned int ssi0_data_mux[] = {
3688 SSI_SDATA0_MARK,
3689};
3690static const unsigned int ssi01239_ctrl_pins[] = {
3691 /* SCK, WS */
3692 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3693};
3694static const unsigned int ssi01239_ctrl_mux[] = {
3695 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3696};
3697static const unsigned int ssi1_data_a_pins[] = {
3698 /* SDATA */
3699 RCAR_GP_PIN(6, 3),
3700};
3701static const unsigned int ssi1_data_a_mux[] = {
3702 SSI_SDATA1_A_MARK,
3703};
3704static const unsigned int ssi1_data_b_pins[] = {
3705 /* SDATA */
3706 RCAR_GP_PIN(5, 12),
3707};
3708static const unsigned int ssi1_data_b_mux[] = {
3709 SSI_SDATA1_B_MARK,
3710};
3711static const unsigned int ssi1_ctrl_a_pins[] = {
3712 /* SCK, WS */
3713 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3714};
3715static const unsigned int ssi1_ctrl_a_mux[] = {
3716 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3717};
3718static const unsigned int ssi1_ctrl_b_pins[] = {
3719 /* SCK, WS */
3720 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3721};
3722static const unsigned int ssi1_ctrl_b_mux[] = {
3723 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3724};
3725static const unsigned int ssi2_data_a_pins[] = {
3726 /* SDATA */
3727 RCAR_GP_PIN(6, 4),
3728};
3729static const unsigned int ssi2_data_a_mux[] = {
3730 SSI_SDATA2_A_MARK,
3731};
3732static const unsigned int ssi2_data_b_pins[] = {
3733 /* SDATA */
3734 RCAR_GP_PIN(5, 13),
3735};
3736static const unsigned int ssi2_data_b_mux[] = {
3737 SSI_SDATA2_B_MARK,
3738};
3739static const unsigned int ssi2_ctrl_a_pins[] = {
3740 /* SCK, WS */
3741 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3742};
3743static const unsigned int ssi2_ctrl_a_mux[] = {
3744 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3745};
3746static const unsigned int ssi2_ctrl_b_pins[] = {
3747 /* SCK, WS */
3748 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3749};
3750static const unsigned int ssi2_ctrl_b_mux[] = {
3751 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3752};
3753static const unsigned int ssi3_data_pins[] = {
3754 /* SDATA */
3755 RCAR_GP_PIN(6, 7),
3756};
3757static const unsigned int ssi3_data_mux[] = {
3758 SSI_SDATA3_MARK,
3759};
3760static const unsigned int ssi349_ctrl_pins[] = {
3761 /* SCK, WS */
3762 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3763};
3764static const unsigned int ssi349_ctrl_mux[] = {
3765 SSI_SCK349_MARK, SSI_WS349_MARK,
3766};
3767static const unsigned int ssi4_data_pins[] = {
3768 /* SDATA */
3769 RCAR_GP_PIN(6, 10),
3770};
3771static const unsigned int ssi4_data_mux[] = {
3772 SSI_SDATA4_MARK,
3773};
3774static const unsigned int ssi4_ctrl_pins[] = {
3775 /* SCK, WS */
3776 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3777};
3778static const unsigned int ssi4_ctrl_mux[] = {
3779 SSI_SCK4_MARK, SSI_WS4_MARK,
3780};
3781static const unsigned int ssi5_data_pins[] = {
3782 /* SDATA */
3783 RCAR_GP_PIN(6, 13),
3784};
3785static const unsigned int ssi5_data_mux[] = {
3786 SSI_SDATA5_MARK,
3787};
3788static const unsigned int ssi5_ctrl_pins[] = {
3789 /* SCK, WS */
3790 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3791};
3792static const unsigned int ssi5_ctrl_mux[] = {
3793 SSI_SCK5_MARK, SSI_WS5_MARK,
3794};
3795static const unsigned int ssi6_data_pins[] = {
3796 /* SDATA */
3797 RCAR_GP_PIN(6, 16),
3798};
3799static const unsigned int ssi6_data_mux[] = {
3800 SSI_SDATA6_MARK,
3801};
3802static const unsigned int ssi6_ctrl_pins[] = {
3803 /* SCK, WS */
3804 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3805};
3806static const unsigned int ssi6_ctrl_mux[] = {
3807 SSI_SCK6_MARK, SSI_WS6_MARK,
3808};
3809static const unsigned int ssi7_data_pins[] = {
3810 /* SDATA */
3811 RCAR_GP_PIN(6, 19),
3812};
3813static const unsigned int ssi7_data_mux[] = {
3814 SSI_SDATA7_MARK,
3815};
3816static const unsigned int ssi78_ctrl_pins[] = {
3817 /* SCK, WS */
3818 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3819};
3820static const unsigned int ssi78_ctrl_mux[] = {
3821 SSI_SCK78_MARK, SSI_WS78_MARK,
3822};
3823static const unsigned int ssi8_data_pins[] = {
3824 /* SDATA */
3825 RCAR_GP_PIN(6, 20),
3826};
3827static const unsigned int ssi8_data_mux[] = {
3828 SSI_SDATA8_MARK,
3829};
3830static const unsigned int ssi9_data_a_pins[] = {
3831 /* SDATA */
3832 RCAR_GP_PIN(6, 21),
3833};
3834static const unsigned int ssi9_data_a_mux[] = {
3835 SSI_SDATA9_A_MARK,
3836};
3837static const unsigned int ssi9_data_b_pins[] = {
3838 /* SDATA */
3839 RCAR_GP_PIN(5, 14),
3840};
3841static const unsigned int ssi9_data_b_mux[] = {
3842 SSI_SDATA9_B_MARK,
3843};
3844static const unsigned int ssi9_ctrl_a_pins[] = {
3845 /* SCK, WS */
3846 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3847};
3848static const unsigned int ssi9_ctrl_a_mux[] = {
3849 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3850};
3851static const unsigned int ssi9_ctrl_b_pins[] = {
3852 /* SCK, WS */
3853 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3854};
3855static const unsigned int ssi9_ctrl_b_mux[] = {
3856 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3857};
3858
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3859/* - TMU -------------------------------------------------------------------- */
3860static const unsigned int tmu_tclk1_a_pins[] = {
3861 /* TCLK */
3862 RCAR_GP_PIN(6, 23),
3863};
3864static const unsigned int tmu_tclk1_a_mux[] = {
3865 TCLK1_A_MARK,
3866};
3867static const unsigned int tmu_tclk1_b_pins[] = {
3868 /* TCLK */
3869 RCAR_GP_PIN(5, 19),
3870};
3871static const unsigned int tmu_tclk1_b_mux[] = {
3872 TCLK1_B_MARK,
3873};
3874static const unsigned int tmu_tclk2_a_pins[] = {
3875 /* TCLK */
3876 RCAR_GP_PIN(6, 19),
3877};
3878static const unsigned int tmu_tclk2_a_mux[] = {
3879 TCLK2_A_MARK,
3880};
3881static const unsigned int tmu_tclk2_b_pins[] = {
3882 /* TCLK */
3883 RCAR_GP_PIN(6, 28),
3884};
3885static const unsigned int tmu_tclk2_b_mux[] = {
3886 TCLK2_B_MARK,
3887};
3888
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3889/* - TPU ------------------------------------------------------------------- */
3890static const unsigned int tpu_to0_pins[] = {
3891 /* TPU0TO0 */
3892 RCAR_GP_PIN(6, 28),
3893};
3894static const unsigned int tpu_to0_mux[] = {
3895 TPU0TO0_MARK,
3896};
3897static const unsigned int tpu_to1_pins[] = {
3898 /* TPU0TO1 */
3899 RCAR_GP_PIN(6, 29),
3900};
3901static const unsigned int tpu_to1_mux[] = {
3902 TPU0TO1_MARK,
3903};
3904static const unsigned int tpu_to2_pins[] = {
3905 /* TPU0TO2 */
3906 RCAR_GP_PIN(6, 30),
3907};
3908static const unsigned int tpu_to2_mux[] = {
3909 TPU0TO2_MARK,
3910};
3911static const unsigned int tpu_to3_pins[] = {
3912 /* TPU0TO3 */
3913 RCAR_GP_PIN(6, 31),
3914};
3915static const unsigned int tpu_to3_mux[] = {
3916 TPU0TO3_MARK,
3917};
3918
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3919/* - USB0 ------------------------------------------------------------------- */
3920static const unsigned int usb0_pins[] = {
3921 /* PWEN, OVC */
3922 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3923};
3924static const unsigned int usb0_mux[] = {
3925 USB0_PWEN_MARK, USB0_OVC_MARK,
3926};
3927/* - USB1 ------------------------------------------------------------------- */
3928static const unsigned int usb1_pins[] = {
3929 /* PWEN, OVC */
3930 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3931};
3932static const unsigned int usb1_mux[] = {
3933 USB1_PWEN_MARK, USB1_OVC_MARK,
3934};
3935
3936/* - USB30 ------------------------------------------------------------------ */
3937static const unsigned int usb30_pins[] = {
3938 /* PWEN, OVC */
3939 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3940};
3941static const unsigned int usb30_mux[] = {
3942 USB30_PWEN_MARK, USB30_OVC_MARK,
3943};
3944
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3945/* - VIN4 ------------------------------------------------------------------- */
3946static const unsigned int vin4_data18_a_pins[] = {
3947 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3948 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3949 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3950 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3951 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3952 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3953 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3954 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3955 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3956};
3957static const unsigned int vin4_data18_a_mux[] = {
3958 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3959 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3960 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3961 VI4_DATA10_MARK, VI4_DATA11_MARK,
3962 VI4_DATA12_MARK, VI4_DATA13_MARK,
3963 VI4_DATA14_MARK, VI4_DATA15_MARK,
3964 VI4_DATA18_MARK, VI4_DATA19_MARK,
3965 VI4_DATA20_MARK, VI4_DATA21_MARK,
3966 VI4_DATA22_MARK, VI4_DATA23_MARK,
3967};
3968static const unsigned int vin4_data18_b_pins[] = {
3969 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3970 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3971 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3972 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3973 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3974 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3975 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3976 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3977 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3978};
3979static const unsigned int vin4_data18_b_mux[] = {
3980 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3981 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3982 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3983 VI4_DATA10_MARK, VI4_DATA11_MARK,
3984 VI4_DATA12_MARK, VI4_DATA13_MARK,
3985 VI4_DATA14_MARK, VI4_DATA15_MARK,
3986 VI4_DATA18_MARK, VI4_DATA19_MARK,
3987 VI4_DATA20_MARK, VI4_DATA21_MARK,
3988 VI4_DATA22_MARK, VI4_DATA23_MARK,
3989};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]3990static const unsigned int vin4_data_a_pins[] = {
3991 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3992 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3993 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3994 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3995 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3996 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3997 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3998 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3999 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4000 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4001 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4002 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4003};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4004static const unsigned int vin4_data_a_mux[] = {
4005 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4006 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4007 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4008 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4009 VI4_DATA8_MARK, VI4_DATA9_MARK,
4010 VI4_DATA10_MARK, VI4_DATA11_MARK,
4011 VI4_DATA12_MARK, VI4_DATA13_MARK,
4012 VI4_DATA14_MARK, VI4_DATA15_MARK,
4013 VI4_DATA16_MARK, VI4_DATA17_MARK,
4014 VI4_DATA18_MARK, VI4_DATA19_MARK,
4015 VI4_DATA20_MARK, VI4_DATA21_MARK,
4016 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4017};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4018static const unsigned int vin4_data_b_pins[] = {
4019 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4020 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4021 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4022 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4023 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4024 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4025 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4026 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4027 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4028 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4029 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4030 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4031};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4032static const unsigned int vin4_data_b_mux[] = {
4033 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4034 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4035 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4036 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4037 VI4_DATA8_MARK, VI4_DATA9_MARK,
4038 VI4_DATA10_MARK, VI4_DATA11_MARK,
4039 VI4_DATA12_MARK, VI4_DATA13_MARK,
4040 VI4_DATA14_MARK, VI4_DATA15_MARK,
4041 VI4_DATA16_MARK, VI4_DATA17_MARK,
4042 VI4_DATA18_MARK, VI4_DATA19_MARK,
4043 VI4_DATA20_MARK, VI4_DATA21_MARK,
4044 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4045};
4046static const unsigned int vin4_sync_pins[] = {
4047 /* HSYNC#, VSYNC# */
4048 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4049};
4050static const unsigned int vin4_sync_mux[] = {
4051 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4052};
4053static const unsigned int vin4_field_pins[] = {
4054 /* FIELD */
4055 RCAR_GP_PIN(1, 16),
4056};
4057static const unsigned int vin4_field_mux[] = {
4058 VI4_FIELD_MARK,
4059};
4060static const unsigned int vin4_clkenb_pins[] = {
4061 /* CLKENB */
4062 RCAR_GP_PIN(1, 19),
4063};
4064static const unsigned int vin4_clkenb_mux[] = {
4065 VI4_CLKENB_MARK,
4066};
4067static const unsigned int vin4_clk_pins[] = {
4068 /* CLK */
4069 RCAR_GP_PIN(1, 27),
4070};
4071static const unsigned int vin4_clk_mux[] = {
4072 VI4_CLK_MARK,
4073};
4074
4075/* - VIN5 ------------------------------------------------------------------- */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4076static const unsigned int vin5_data_pins[] = {
4077 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4078 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4079 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4080 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4081 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4082 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4083 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4084 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4085};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4086static const unsigned int vin5_data_mux[] = {
4087 VI5_DATA0_MARK, VI5_DATA1_MARK,
4088 VI5_DATA2_MARK, VI5_DATA3_MARK,
4089 VI5_DATA4_MARK, VI5_DATA5_MARK,
4090 VI5_DATA6_MARK, VI5_DATA7_MARK,
4091 VI5_DATA8_MARK, VI5_DATA9_MARK,
4092 VI5_DATA10_MARK, VI5_DATA11_MARK,
4093 VI5_DATA12_MARK, VI5_DATA13_MARK,
4094 VI5_DATA14_MARK, VI5_DATA15_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4095};
4096static const unsigned int vin5_sync_pins[] = {
4097 /* HSYNC#, VSYNC# */
4098 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4099};
4100static const unsigned int vin5_sync_mux[] = {
4101 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4102};
4103static const unsigned int vin5_field_pins[] = {
4104 RCAR_GP_PIN(1, 11),
4105};
4106static const unsigned int vin5_field_mux[] = {
4107 /* FIELD */
4108 VI5_FIELD_MARK,
4109};
4110static const unsigned int vin5_clkenb_pins[] = {
4111 RCAR_GP_PIN(1, 20),
4112};
4113static const unsigned int vin5_clkenb_mux[] = {
4114 /* CLKENB */
4115 VI5_CLKENB_MARK,
4116};
4117static const unsigned int vin5_clk_pins[] = {
4118 RCAR_GP_PIN(1, 21),
4119};
4120static const unsigned int vin5_clk_mux[] = {
4121 /* CLK */
4122 VI5_CLK_MARK,
4123};
4124
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4125static const struct {
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4126 struct sh_pfc_pin_group common[324];
4127#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4128 struct sh_pfc_pin_group automotive[31];
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]4129#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4130} pinmux_groups = {
4131 .common = {
4132 SH_PFC_PIN_GROUP(audio_clk_a_a),
4133 SH_PFC_PIN_GROUP(audio_clk_a_b),
4134 SH_PFC_PIN_GROUP(audio_clk_a_c),
4135 SH_PFC_PIN_GROUP(audio_clk_b_a),
4136 SH_PFC_PIN_GROUP(audio_clk_b_b),
4137 SH_PFC_PIN_GROUP(audio_clk_c_a),
4138 SH_PFC_PIN_GROUP(audio_clk_c_b),
4139 SH_PFC_PIN_GROUP(audio_clkout_a),
4140 SH_PFC_PIN_GROUP(audio_clkout_b),
4141 SH_PFC_PIN_GROUP(audio_clkout_c),
4142 SH_PFC_PIN_GROUP(audio_clkout_d),
4143 SH_PFC_PIN_GROUP(audio_clkout1_a),
4144 SH_PFC_PIN_GROUP(audio_clkout1_b),
4145 SH_PFC_PIN_GROUP(audio_clkout2_a),
4146 SH_PFC_PIN_GROUP(audio_clkout2_b),
4147 SH_PFC_PIN_GROUP(audio_clkout3_a),
4148 SH_PFC_PIN_GROUP(audio_clkout3_b),
4149 SH_PFC_PIN_GROUP(avb_link),
4150 SH_PFC_PIN_GROUP(avb_magic),
4151 SH_PFC_PIN_GROUP(avb_phy_int),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4152 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4153 SH_PFC_PIN_GROUP(avb_mdio),
4154 SH_PFC_PIN_GROUP(avb_mii),
4155 SH_PFC_PIN_GROUP(avb_avtp_pps),
4156 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4157 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4158 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4159 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4160 SH_PFC_PIN_GROUP(can0_data_a),
4161 SH_PFC_PIN_GROUP(can0_data_b),
4162 SH_PFC_PIN_GROUP(can1_data),
4163 SH_PFC_PIN_GROUP(can_clk),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4164 SH_PFC_PIN_GROUP(canfd0_data_a),
4165 SH_PFC_PIN_GROUP(canfd0_data_b),
4166 SH_PFC_PIN_GROUP(canfd1_data),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4167 SH_PFC_PIN_GROUP(du_rgb666),
4168 SH_PFC_PIN_GROUP(du_rgb888),
4169 SH_PFC_PIN_GROUP(du_clk_out_0),
4170 SH_PFC_PIN_GROUP(du_clk_out_1),
4171 SH_PFC_PIN_GROUP(du_sync),
4172 SH_PFC_PIN_GROUP(du_oddf),
4173 SH_PFC_PIN_GROUP(du_cde),
4174 SH_PFC_PIN_GROUP(du_disp),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4175 SH_PFC_PIN_GROUP(hscif0_data),
4176 SH_PFC_PIN_GROUP(hscif0_clk),
4177 SH_PFC_PIN_GROUP(hscif0_ctrl),
4178 SH_PFC_PIN_GROUP(hscif1_data_a),
4179 SH_PFC_PIN_GROUP(hscif1_clk_a),
4180 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4181 SH_PFC_PIN_GROUP(hscif1_data_b),
4182 SH_PFC_PIN_GROUP(hscif1_clk_b),
4183 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4184 SH_PFC_PIN_GROUP(hscif2_data_a),
4185 SH_PFC_PIN_GROUP(hscif2_clk_a),
4186 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4187 SH_PFC_PIN_GROUP(hscif2_data_b),
4188 SH_PFC_PIN_GROUP(hscif2_clk_b),
4189 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4190 SH_PFC_PIN_GROUP(hscif2_data_c),
4191 SH_PFC_PIN_GROUP(hscif2_clk_c),
4192 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4193 SH_PFC_PIN_GROUP(hscif3_data_a),
4194 SH_PFC_PIN_GROUP(hscif3_clk),
4195 SH_PFC_PIN_GROUP(hscif3_ctrl),
4196 SH_PFC_PIN_GROUP(hscif3_data_b),
4197 SH_PFC_PIN_GROUP(hscif3_data_c),
4198 SH_PFC_PIN_GROUP(hscif3_data_d),
4199 SH_PFC_PIN_GROUP(hscif4_data_a),
4200 SH_PFC_PIN_GROUP(hscif4_clk),
4201 SH_PFC_PIN_GROUP(hscif4_ctrl),
4202 SH_PFC_PIN_GROUP(hscif4_data_b),
4203 SH_PFC_PIN_GROUP(i2c0),
4204 SH_PFC_PIN_GROUP(i2c1_a),
4205 SH_PFC_PIN_GROUP(i2c1_b),
4206 SH_PFC_PIN_GROUP(i2c2_a),
4207 SH_PFC_PIN_GROUP(i2c2_b),
4208 SH_PFC_PIN_GROUP(i2c3),
4209 SH_PFC_PIN_GROUP(i2c5),
4210 SH_PFC_PIN_GROUP(i2c6_a),
4211 SH_PFC_PIN_GROUP(i2c6_b),
4212 SH_PFC_PIN_GROUP(i2c6_c),
4213 SH_PFC_PIN_GROUP(intc_ex_irq0),
4214 SH_PFC_PIN_GROUP(intc_ex_irq1),
4215 SH_PFC_PIN_GROUP(intc_ex_irq2),
4216 SH_PFC_PIN_GROUP(intc_ex_irq3),
4217 SH_PFC_PIN_GROUP(intc_ex_irq4),
4218 SH_PFC_PIN_GROUP(intc_ex_irq5),
4219 SH_PFC_PIN_GROUP(msiof0_clk),
4220 SH_PFC_PIN_GROUP(msiof0_sync),
4221 SH_PFC_PIN_GROUP(msiof0_ss1),
4222 SH_PFC_PIN_GROUP(msiof0_ss2),
4223 SH_PFC_PIN_GROUP(msiof0_txd),
4224 SH_PFC_PIN_GROUP(msiof0_rxd),
4225 SH_PFC_PIN_GROUP(msiof1_clk_a),
4226 SH_PFC_PIN_GROUP(msiof1_sync_a),
4227 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4228 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4229 SH_PFC_PIN_GROUP(msiof1_txd_a),
4230 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4231 SH_PFC_PIN_GROUP(msiof1_clk_b),
4232 SH_PFC_PIN_GROUP(msiof1_sync_b),
4233 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4234 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4235 SH_PFC_PIN_GROUP(msiof1_txd_b),
4236 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4237 SH_PFC_PIN_GROUP(msiof1_clk_c),
4238 SH_PFC_PIN_GROUP(msiof1_sync_c),
4239 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4240 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4241 SH_PFC_PIN_GROUP(msiof1_txd_c),
4242 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4243 SH_PFC_PIN_GROUP(msiof1_clk_d),
4244 SH_PFC_PIN_GROUP(msiof1_sync_d),
4245 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4246 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4247 SH_PFC_PIN_GROUP(msiof1_txd_d),
4248 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4249 SH_PFC_PIN_GROUP(msiof1_clk_e),
4250 SH_PFC_PIN_GROUP(msiof1_sync_e),
4251 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4252 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4253 SH_PFC_PIN_GROUP(msiof1_txd_e),
4254 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4255 SH_PFC_PIN_GROUP(msiof1_clk_f),
4256 SH_PFC_PIN_GROUP(msiof1_sync_f),
4257 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4258 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4259 SH_PFC_PIN_GROUP(msiof1_txd_f),
4260 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4261 SH_PFC_PIN_GROUP(msiof1_clk_g),
4262 SH_PFC_PIN_GROUP(msiof1_sync_g),
4263 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4264 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4265 SH_PFC_PIN_GROUP(msiof1_txd_g),
4266 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4267 SH_PFC_PIN_GROUP(msiof2_clk_a),
4268 SH_PFC_PIN_GROUP(msiof2_sync_a),
4269 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4270 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4271 SH_PFC_PIN_GROUP(msiof2_txd_a),
4272 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4273 SH_PFC_PIN_GROUP(msiof2_clk_b),
4274 SH_PFC_PIN_GROUP(msiof2_sync_b),
4275 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4276 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4277 SH_PFC_PIN_GROUP(msiof2_txd_b),
4278 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4279 SH_PFC_PIN_GROUP(msiof2_clk_c),
4280 SH_PFC_PIN_GROUP(msiof2_sync_c),
4281 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4282 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4283 SH_PFC_PIN_GROUP(msiof2_txd_c),
4284 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4285 SH_PFC_PIN_GROUP(msiof2_clk_d),
4286 SH_PFC_PIN_GROUP(msiof2_sync_d),
4287 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4288 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4289 SH_PFC_PIN_GROUP(msiof2_txd_d),
4290 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4291 SH_PFC_PIN_GROUP(msiof3_clk_a),
4292 SH_PFC_PIN_GROUP(msiof3_sync_a),
4293 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4294 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4295 SH_PFC_PIN_GROUP(msiof3_txd_a),
4296 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4297 SH_PFC_PIN_GROUP(msiof3_clk_b),
4298 SH_PFC_PIN_GROUP(msiof3_sync_b),
4299 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4300 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4301 SH_PFC_PIN_GROUP(msiof3_txd_b),
4302 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4303 SH_PFC_PIN_GROUP(msiof3_clk_c),
4304 SH_PFC_PIN_GROUP(msiof3_sync_c),
4305 SH_PFC_PIN_GROUP(msiof3_txd_c),
4306 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4307 SH_PFC_PIN_GROUP(msiof3_clk_d),
4308 SH_PFC_PIN_GROUP(msiof3_sync_d),
4309 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4310 SH_PFC_PIN_GROUP(msiof3_txd_d),
4311 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4312 SH_PFC_PIN_GROUP(msiof3_clk_e),
4313 SH_PFC_PIN_GROUP(msiof3_sync_e),
4314 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4315 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4316 SH_PFC_PIN_GROUP(msiof3_txd_e),
4317 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4318 SH_PFC_PIN_GROUP(pwm0),
4319 SH_PFC_PIN_GROUP(pwm1_a),
4320 SH_PFC_PIN_GROUP(pwm1_b),
4321 SH_PFC_PIN_GROUP(pwm2_a),
4322 SH_PFC_PIN_GROUP(pwm2_b),
4323 SH_PFC_PIN_GROUP(pwm3_a),
4324 SH_PFC_PIN_GROUP(pwm3_b),
4325 SH_PFC_PIN_GROUP(pwm4_a),
4326 SH_PFC_PIN_GROUP(pwm4_b),
4327 SH_PFC_PIN_GROUP(pwm5_a),
4328 SH_PFC_PIN_GROUP(pwm5_b),
4329 SH_PFC_PIN_GROUP(pwm6_a),
4330 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4331 SH_PFC_PIN_GROUP(qspi0_ctrl),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4332 BUS_DATA_PIN_GROUP(qspi0_data, 2),
4333 BUS_DATA_PIN_GROUP(qspi0_data, 4),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4334 SH_PFC_PIN_GROUP(qspi1_ctrl),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4335 BUS_DATA_PIN_GROUP(qspi1_data, 2),
4336 BUS_DATA_PIN_GROUP(qspi1_data, 4),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4337 SH_PFC_PIN_GROUP(scif0_data),
4338 SH_PFC_PIN_GROUP(scif0_clk),
4339 SH_PFC_PIN_GROUP(scif0_ctrl),
4340 SH_PFC_PIN_GROUP(scif1_data_a),
4341 SH_PFC_PIN_GROUP(scif1_clk),
4342 SH_PFC_PIN_GROUP(scif1_ctrl),
4343 SH_PFC_PIN_GROUP(scif1_data_b),
4344 SH_PFC_PIN_GROUP(scif2_data_a),
4345 SH_PFC_PIN_GROUP(scif2_clk),
4346 SH_PFC_PIN_GROUP(scif2_data_b),
4347 SH_PFC_PIN_GROUP(scif3_data_a),
4348 SH_PFC_PIN_GROUP(scif3_clk),
4349 SH_PFC_PIN_GROUP(scif3_ctrl),
4350 SH_PFC_PIN_GROUP(scif3_data_b),
4351 SH_PFC_PIN_GROUP(scif4_data_a),
4352 SH_PFC_PIN_GROUP(scif4_clk_a),
4353 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4354 SH_PFC_PIN_GROUP(scif4_data_b),
4355 SH_PFC_PIN_GROUP(scif4_clk_b),
4356 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4357 SH_PFC_PIN_GROUP(scif4_data_c),
4358 SH_PFC_PIN_GROUP(scif4_clk_c),
4359 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4360 SH_PFC_PIN_GROUP(scif5_data_a),
4361 SH_PFC_PIN_GROUP(scif5_clk_a),
4362 SH_PFC_PIN_GROUP(scif5_data_b),
4363 SH_PFC_PIN_GROUP(scif5_clk_b),
4364 SH_PFC_PIN_GROUP(scif_clk_a),
4365 SH_PFC_PIN_GROUP(scif_clk_b),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4366 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4367 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4368 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4369 SH_PFC_PIN_GROUP(sdhi0_cd),
4370 SH_PFC_PIN_GROUP(sdhi0_wp),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4371 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4372 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4373 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4374 SH_PFC_PIN_GROUP(sdhi1_cd),
4375 SH_PFC_PIN_GROUP(sdhi1_wp),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4376 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4377 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4378 BUS_DATA_PIN_GROUP(sdhi2_data, 8),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4379 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4380 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4381 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4382 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4383 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4384 SH_PFC_PIN_GROUP(sdhi2_ds),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4385 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4386 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4387 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4388 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4389 SH_PFC_PIN_GROUP(sdhi3_cd),
4390 SH_PFC_PIN_GROUP(sdhi3_wp),
4391 SH_PFC_PIN_GROUP(sdhi3_ds),
4392 SH_PFC_PIN_GROUP(ssi0_data),
4393 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4394 SH_PFC_PIN_GROUP(ssi1_data_a),
4395 SH_PFC_PIN_GROUP(ssi1_data_b),
4396 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4397 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4398 SH_PFC_PIN_GROUP(ssi2_data_a),
4399 SH_PFC_PIN_GROUP(ssi2_data_b),
4400 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4401 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4402 SH_PFC_PIN_GROUP(ssi3_data),
4403 SH_PFC_PIN_GROUP(ssi349_ctrl),
4404 SH_PFC_PIN_GROUP(ssi4_data),
4405 SH_PFC_PIN_GROUP(ssi4_ctrl),
4406 SH_PFC_PIN_GROUP(ssi5_data),
4407 SH_PFC_PIN_GROUP(ssi5_ctrl),
4408 SH_PFC_PIN_GROUP(ssi6_data),
4409 SH_PFC_PIN_GROUP(ssi6_ctrl),
4410 SH_PFC_PIN_GROUP(ssi7_data),
4411 SH_PFC_PIN_GROUP(ssi78_ctrl),
4412 SH_PFC_PIN_GROUP(ssi8_data),
4413 SH_PFC_PIN_GROUP(ssi9_data_a),
4414 SH_PFC_PIN_GROUP(ssi9_data_b),
4415 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4416 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4417 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4418 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4419 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4420 SH_PFC_PIN_GROUP(tmu_tclk2_b),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4421 SH_PFC_PIN_GROUP(tpu_to0),
4422 SH_PFC_PIN_GROUP(tpu_to1),
4423 SH_PFC_PIN_GROUP(tpu_to2),
4424 SH_PFC_PIN_GROUP(tpu_to3),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4425 SH_PFC_PIN_GROUP(usb0),
4426 SH_PFC_PIN_GROUP(usb1),
4427 SH_PFC_PIN_GROUP(usb30),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4428 BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4429 BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4430 BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4431 BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4432 SH_PFC_PIN_GROUP(vin4_data18_a),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4433 BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4434 BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4435 BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4436 BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4437 BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4438 BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4439 SH_PFC_PIN_GROUP(vin4_data18_b),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4440 BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4441 BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4442 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4443 SH_PFC_PIN_GROUP(vin4_sync),
4444 SH_PFC_PIN_GROUP(vin4_field),
4445 SH_PFC_PIN_GROUP(vin4_clkenb),
4446 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4447 BUS_DATA_PIN_GROUP(vin5_data, 8),
4448 BUS_DATA_PIN_GROUP(vin5_data, 10),
4449 BUS_DATA_PIN_GROUP(vin5_data, 12),
4450 BUS_DATA_PIN_GROUP(vin5_data, 16),
4451 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4452 SH_PFC_PIN_GROUP(vin5_sync),
4453 SH_PFC_PIN_GROUP(vin5_field),
4454 SH_PFC_PIN_GROUP(vin5_clkenb),
4455 SH_PFC_PIN_GROUP(vin5_clk),
4456 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4457#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4458 .automotive = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4459 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4460 SH_PFC_PIN_GROUP(drif0_data0_a),
4461 SH_PFC_PIN_GROUP(drif0_data1_a),
4462 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4463 SH_PFC_PIN_GROUP(drif0_data0_b),
4464 SH_PFC_PIN_GROUP(drif0_data1_b),
4465 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4466 SH_PFC_PIN_GROUP(drif0_data0_c),
4467 SH_PFC_PIN_GROUP(drif0_data1_c),
4468 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4469 SH_PFC_PIN_GROUP(drif1_data0_a),
4470 SH_PFC_PIN_GROUP(drif1_data1_a),
4471 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4472 SH_PFC_PIN_GROUP(drif1_data0_b),
4473 SH_PFC_PIN_GROUP(drif1_data1_b),
4474 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4475 SH_PFC_PIN_GROUP(drif1_data0_c),
4476 SH_PFC_PIN_GROUP(drif1_data1_c),
4477 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4478 SH_PFC_PIN_GROUP(drif2_data0_a),
4479 SH_PFC_PIN_GROUP(drif2_data1_a),
4480 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4481 SH_PFC_PIN_GROUP(drif2_data0_b),
4482 SH_PFC_PIN_GROUP(drif2_data1_b),
4483 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4484 SH_PFC_PIN_GROUP(drif3_data0_a),
4485 SH_PFC_PIN_GROUP(drif3_data1_a),
4486 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4487 SH_PFC_PIN_GROUP(drif3_data0_b),
4488 SH_PFC_PIN_GROUP(drif3_data1_b),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4489 SH_PFC_PIN_GROUP(mlb_3pin),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4490 }
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4491#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4492};
4493
4494static const char * const audio_clk_groups[] = {
4495 "audio_clk_a_a",
4496 "audio_clk_a_b",
4497 "audio_clk_a_c",
4498 "audio_clk_b_a",
4499 "audio_clk_b_b",
4500 "audio_clk_c_a",
4501 "audio_clk_c_b",
4502 "audio_clkout_a",
4503 "audio_clkout_b",
4504 "audio_clkout_c",
4505 "audio_clkout_d",
4506 "audio_clkout1_a",
4507 "audio_clkout1_b",
4508 "audio_clkout2_a",
4509 "audio_clkout2_b",
4510 "audio_clkout3_a",
4511 "audio_clkout3_b",
4512};
4513
4514static const char * const avb_groups[] = {
4515 "avb_link",
4516 "avb_magic",
4517 "avb_phy_int",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4518 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4519 "avb_mdio",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4520 "avb_mii",
4521 "avb_avtp_pps",
4522 "avb_avtp_match_a",
4523 "avb_avtp_capture_a",
4524 "avb_avtp_match_b",
4525 "avb_avtp_capture_b",
4526};
4527
4528static const char * const can0_groups[] = {
4529 "can0_data_a",
4530 "can0_data_b",
4531};
4532
4533static const char * const can1_groups[] = {
4534 "can1_data",
4535};
4536
4537static const char * const can_clk_groups[] = {
4538 "can_clk",
4539};
4540
4541static const char * const canfd0_groups[] = {
4542 "canfd0_data_a",
4543 "canfd0_data_b",
4544};
4545
4546static const char * const canfd1_groups[] = {
4547 "canfd1_data",
4548};
4549
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4550#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4551static const char * const drif0_groups[] = {
4552 "drif0_ctrl_a",
4553 "drif0_data0_a",
4554 "drif0_data1_a",
4555 "drif0_ctrl_b",
4556 "drif0_data0_b",
4557 "drif0_data1_b",
4558 "drif0_ctrl_c",
4559 "drif0_data0_c",
4560 "drif0_data1_c",
4561};
4562
4563static const char * const drif1_groups[] = {
4564 "drif1_ctrl_a",
4565 "drif1_data0_a",
4566 "drif1_data1_a",
4567 "drif1_ctrl_b",
4568 "drif1_data0_b",
4569 "drif1_data1_b",
4570 "drif1_ctrl_c",
4571 "drif1_data0_c",
4572 "drif1_data1_c",
4573};
4574
4575static const char * const drif2_groups[] = {
4576 "drif2_ctrl_a",
4577 "drif2_data0_a",
4578 "drif2_data1_a",
4579 "drif2_ctrl_b",
4580 "drif2_data0_b",
4581 "drif2_data1_b",
4582};
4583
4584static const char * const drif3_groups[] = {
4585 "drif3_ctrl_a",
4586 "drif3_data0_a",
4587 "drif3_data1_a",
4588 "drif3_ctrl_b",
4589 "drif3_data0_b",
4590 "drif3_data1_b",
4591};
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4592#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4593
4594static const char * const du_groups[] = {
4595 "du_rgb666",
4596 "du_rgb888",
4597 "du_clk_out_0",
4598 "du_clk_out_1",
4599 "du_sync",
4600 "du_oddf",
4601 "du_cde",
4602 "du_disp",
4603};
4604
4605static const char * const hscif0_groups[] = {
4606 "hscif0_data",
4607 "hscif0_clk",
4608 "hscif0_ctrl",
4609};
4610
4611static const char * const hscif1_groups[] = {
4612 "hscif1_data_a",
4613 "hscif1_clk_a",
4614 "hscif1_ctrl_a",
4615 "hscif1_data_b",
4616 "hscif1_clk_b",
4617 "hscif1_ctrl_b",
4618};
4619
4620static const char * const hscif2_groups[] = {
4621 "hscif2_data_a",
4622 "hscif2_clk_a",
4623 "hscif2_ctrl_a",
4624 "hscif2_data_b",
4625 "hscif2_clk_b",
4626 "hscif2_ctrl_b",
4627 "hscif2_data_c",
4628 "hscif2_clk_c",
4629 "hscif2_ctrl_c",
4630};
4631
4632static const char * const hscif3_groups[] = {
4633 "hscif3_data_a",
4634 "hscif3_clk",
4635 "hscif3_ctrl",
4636 "hscif3_data_b",
4637 "hscif3_data_c",
4638 "hscif3_data_d",
4639};
4640
4641static const char * const hscif4_groups[] = {
4642 "hscif4_data_a",
4643 "hscif4_clk",
4644 "hscif4_ctrl",
4645 "hscif4_data_b",
4646};
4647
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4648static const char * const i2c0_groups[] = {
4649 "i2c0",
4650};
4651
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4652static const char * const i2c1_groups[] = {
4653 "i2c1_a",
4654 "i2c1_b",
4655};
4656
4657static const char * const i2c2_groups[] = {
4658 "i2c2_a",
4659 "i2c2_b",
4660};
4661
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4662static const char * const i2c3_groups[] = {
4663 "i2c3",
4664};
4665
4666static const char * const i2c5_groups[] = {
4667 "i2c5",
4668};
4669
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4670static const char * const i2c6_groups[] = {
4671 "i2c6_a",
4672 "i2c6_b",
4673 "i2c6_c",
4674};
4675
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4676static const char * const intc_ex_groups[] = {
4677 "intc_ex_irq0",
4678 "intc_ex_irq1",
4679 "intc_ex_irq2",
4680 "intc_ex_irq3",
4681 "intc_ex_irq4",
4682 "intc_ex_irq5",
4683};
4684
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]4685#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4686static const char * const mlb_3pin_groups[] = {
4687 "mlb_3pin",
4688};
4689#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4690
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4691static const char * const msiof0_groups[] = {
4692 "msiof0_clk",
4693 "msiof0_sync",
4694 "msiof0_ss1",
4695 "msiof0_ss2",
4696 "msiof0_txd",
4697 "msiof0_rxd",
4698};
4699
4700static const char * const msiof1_groups[] = {
4701 "msiof1_clk_a",
4702 "msiof1_sync_a",
4703 "msiof1_ss1_a",
4704 "msiof1_ss2_a",
4705 "msiof1_txd_a",
4706 "msiof1_rxd_a",
4707 "msiof1_clk_b",
4708 "msiof1_sync_b",
4709 "msiof1_ss1_b",
4710 "msiof1_ss2_b",
4711 "msiof1_txd_b",
4712 "msiof1_rxd_b",
4713 "msiof1_clk_c",
4714 "msiof1_sync_c",
4715 "msiof1_ss1_c",
4716 "msiof1_ss2_c",
4717 "msiof1_txd_c",
4718 "msiof1_rxd_c",
4719 "msiof1_clk_d",
4720 "msiof1_sync_d",
4721 "msiof1_ss1_d",
4722 "msiof1_ss2_d",
4723 "msiof1_txd_d",
4724 "msiof1_rxd_d",
4725 "msiof1_clk_e",
4726 "msiof1_sync_e",
4727 "msiof1_ss1_e",
4728 "msiof1_ss2_e",
4729 "msiof1_txd_e",
4730 "msiof1_rxd_e",
4731 "msiof1_clk_f",
4732 "msiof1_sync_f",
4733 "msiof1_ss1_f",
4734 "msiof1_ss2_f",
4735 "msiof1_txd_f",
4736 "msiof1_rxd_f",
4737 "msiof1_clk_g",
4738 "msiof1_sync_g",
4739 "msiof1_ss1_g",
4740 "msiof1_ss2_g",
4741 "msiof1_txd_g",
4742 "msiof1_rxd_g",
4743};
4744
4745static const char * const msiof2_groups[] = {
4746 "msiof2_clk_a",
4747 "msiof2_sync_a",
4748 "msiof2_ss1_a",
4749 "msiof2_ss2_a",
4750 "msiof2_txd_a",
4751 "msiof2_rxd_a",
4752 "msiof2_clk_b",
4753 "msiof2_sync_b",
4754 "msiof2_ss1_b",
4755 "msiof2_ss2_b",
4756 "msiof2_txd_b",
4757 "msiof2_rxd_b",
4758 "msiof2_clk_c",
4759 "msiof2_sync_c",
4760 "msiof2_ss1_c",
4761 "msiof2_ss2_c",
4762 "msiof2_txd_c",
4763 "msiof2_rxd_c",
4764 "msiof2_clk_d",
4765 "msiof2_sync_d",
4766 "msiof2_ss1_d",
4767 "msiof2_ss2_d",
4768 "msiof2_txd_d",
4769 "msiof2_rxd_d",
4770};
4771
4772static const char * const msiof3_groups[] = {
4773 "msiof3_clk_a",
4774 "msiof3_sync_a",
4775 "msiof3_ss1_a",
4776 "msiof3_ss2_a",
4777 "msiof3_txd_a",
4778 "msiof3_rxd_a",
4779 "msiof3_clk_b",
4780 "msiof3_sync_b",
4781 "msiof3_ss1_b",
4782 "msiof3_ss2_b",
4783 "msiof3_txd_b",
4784 "msiof3_rxd_b",
4785 "msiof3_clk_c",
4786 "msiof3_sync_c",
4787 "msiof3_txd_c",
4788 "msiof3_rxd_c",
4789 "msiof3_clk_d",
4790 "msiof3_sync_d",
4791 "msiof3_ss1_d",
4792 "msiof3_txd_d",
4793 "msiof3_rxd_d",
4794 "msiof3_clk_e",
4795 "msiof3_sync_e",
4796 "msiof3_ss1_e",
4797 "msiof3_ss2_e",
4798 "msiof3_txd_e",
4799 "msiof3_rxd_e",
4800};
4801
4802static const char * const pwm0_groups[] = {
4803 "pwm0",
4804};
4805
4806static const char * const pwm1_groups[] = {
4807 "pwm1_a",
4808 "pwm1_b",
4809};
4810
4811static const char * const pwm2_groups[] = {
4812 "pwm2_a",
4813 "pwm2_b",
4814};
4815
4816static const char * const pwm3_groups[] = {
4817 "pwm3_a",
4818 "pwm3_b",
4819};
4820
4821static const char * const pwm4_groups[] = {
4822 "pwm4_a",
4823 "pwm4_b",
4824};
4825
4826static const char * const pwm5_groups[] = {
4827 "pwm5_a",
4828 "pwm5_b",
4829};
4830
4831static const char * const pwm6_groups[] = {
4832 "pwm6_a",
4833 "pwm6_b",
4834};
4835
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4836static const char * const qspi0_groups[] = {
4837 "qspi0_ctrl",
4838 "qspi0_data2",
4839 "qspi0_data4",
4840};
4841
4842static const char * const qspi1_groups[] = {
4843 "qspi1_ctrl",
4844 "qspi1_data2",
4845 "qspi1_data4",
4846};
4847
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4848static const char * const scif0_groups[] = {
4849 "scif0_data",
4850 "scif0_clk",
4851 "scif0_ctrl",
4852};
4853
4854static const char * const scif1_groups[] = {
4855 "scif1_data_a",
4856 "scif1_clk",
4857 "scif1_ctrl",
4858 "scif1_data_b",
4859};
4860
4861static const char * const scif2_groups[] = {
4862 "scif2_data_a",
4863 "scif2_clk",
4864 "scif2_data_b",
4865};
4866
4867static const char * const scif3_groups[] = {
4868 "scif3_data_a",
4869 "scif3_clk",
4870 "scif3_ctrl",
4871 "scif3_data_b",
4872};
4873
4874static const char * const scif4_groups[] = {
4875 "scif4_data_a",
4876 "scif4_clk_a",
4877 "scif4_ctrl_a",
4878 "scif4_data_b",
4879 "scif4_clk_b",
4880 "scif4_ctrl_b",
4881 "scif4_data_c",
4882 "scif4_clk_c",
4883 "scif4_ctrl_c",
4884};
4885
4886static const char * const scif5_groups[] = {
4887 "scif5_data_a",
4888 "scif5_clk_a",
4889 "scif5_data_b",
4890 "scif5_clk_b",
4891};
4892
4893static const char * const scif_clk_groups[] = {
4894 "scif_clk_a",
4895 "scif_clk_b",
4896};
4897
4898static const char * const sdhi0_groups[] = {
4899 "sdhi0_data1",
4900 "sdhi0_data4",
4901 "sdhi0_ctrl",
4902 "sdhi0_cd",
4903 "sdhi0_wp",
4904};
4905
4906static const char * const sdhi1_groups[] = {
4907 "sdhi1_data1",
4908 "sdhi1_data4",
4909 "sdhi1_ctrl",
4910 "sdhi1_cd",
4911 "sdhi1_wp",
4912};
4913
4914static const char * const sdhi2_groups[] = {
4915 "sdhi2_data1",
4916 "sdhi2_data4",
4917 "sdhi2_data8",
4918 "sdhi2_ctrl",
4919 "sdhi2_cd_a",
4920 "sdhi2_wp_a",
4921 "sdhi2_cd_b",
4922 "sdhi2_wp_b",
4923 "sdhi2_ds",
4924};
4925
4926static const char * const sdhi3_groups[] = {
4927 "sdhi3_data1",
4928 "sdhi3_data4",
4929 "sdhi3_data8",
4930 "sdhi3_ctrl",
4931 "sdhi3_cd",
4932 "sdhi3_wp",
4933 "sdhi3_ds",
4934};
4935
4936static const char * const ssi_groups[] = {
4937 "ssi0_data",
4938 "ssi01239_ctrl",
4939 "ssi1_data_a",
4940 "ssi1_data_b",
4941 "ssi1_ctrl_a",
4942 "ssi1_ctrl_b",
4943 "ssi2_data_a",
4944 "ssi2_data_b",
4945 "ssi2_ctrl_a",
4946 "ssi2_ctrl_b",
4947 "ssi3_data",
4948 "ssi349_ctrl",
4949 "ssi4_data",
4950 "ssi4_ctrl",
4951 "ssi5_data",
4952 "ssi5_ctrl",
4953 "ssi6_data",
4954 "ssi6_ctrl",
4955 "ssi7_data",
4956 "ssi78_ctrl",
4957 "ssi8_data",
4958 "ssi9_data_a",
4959 "ssi9_data_b",
4960 "ssi9_ctrl_a",
4961 "ssi9_ctrl_b",
4962};
4963
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4964static const char * const tmu_groups[] = {
4965 "tmu_tclk1_a",
4966 "tmu_tclk1_b",
4967 "tmu_tclk2_a",
4968 "tmu_tclk2_b",
4969};
4970
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4971static const char * const tpu_groups[] = {
4972 "tpu_to0",
4973 "tpu_to1",
4974 "tpu_to2",
4975 "tpu_to3",
4976};
4977
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4978static const char * const usb0_groups[] = {
4979 "usb0",
4980};
4981
4982static const char * const usb1_groups[] = {
4983 "usb1",
4984};
4985
4986static const char * const usb30_groups[] = {
4987 "usb30",
4988};
4989
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4990static const char * const vin4_groups[] = {
4991 "vin4_data8_a",
4992 "vin4_data10_a",
4993 "vin4_data12_a",
4994 "vin4_data16_a",
4995 "vin4_data18_a",
4996 "vin4_data20_a",
4997 "vin4_data24_a",
4998 "vin4_data8_b",
4999 "vin4_data10_b",
5000 "vin4_data12_b",
5001 "vin4_data16_b",
5002 "vin4_data18_b",
5003 "vin4_data20_b",
5004 "vin4_data24_b",
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5005 "vin4_g8",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5006 "vin4_sync",
5007 "vin4_field",
5008 "vin4_clkenb",
5009 "vin4_clk",
5010};
5011
5012static const char * const vin5_groups[] = {
5013 "vin5_data8",
5014 "vin5_data10",
5015 "vin5_data12",
5016 "vin5_data16",
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5017 "vin5_high8",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5018 "vin5_sync",
5019 "vin5_field",
5020 "vin5_clkenb",
5021 "vin5_clk",
5022};
5023
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5024static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5025 struct sh_pfc_function common[52];
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5026#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5027 struct sh_pfc_function automotive[5];
Biju Dasfd37ab32020-10-28 10:34:23 +0000[diff] [blame]5028#endif
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5029} pinmux_functions = {
5030 .common = {
5031 SH_PFC_FUNCTION(audio_clk),
5032 SH_PFC_FUNCTION(avb),
5033 SH_PFC_FUNCTION(can0),
5034 SH_PFC_FUNCTION(can1),
5035 SH_PFC_FUNCTION(can_clk),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5036 SH_PFC_FUNCTION(canfd0),
5037 SH_PFC_FUNCTION(canfd1),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5038 SH_PFC_FUNCTION(du),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5039 SH_PFC_FUNCTION(hscif0),
5040 SH_PFC_FUNCTION(hscif1),
5041 SH_PFC_FUNCTION(hscif2),
5042 SH_PFC_FUNCTION(hscif3),
5043 SH_PFC_FUNCTION(hscif4),
5044 SH_PFC_FUNCTION(i2c0),
5045 SH_PFC_FUNCTION(i2c1),
5046 SH_PFC_FUNCTION(i2c2),
5047 SH_PFC_FUNCTION(i2c3),
5048 SH_PFC_FUNCTION(i2c5),
5049 SH_PFC_FUNCTION(i2c6),
5050 SH_PFC_FUNCTION(intc_ex),
5051 SH_PFC_FUNCTION(msiof0),
5052 SH_PFC_FUNCTION(msiof1),
5053 SH_PFC_FUNCTION(msiof2),
5054 SH_PFC_FUNCTION(msiof3),
5055 SH_PFC_FUNCTION(pwm0),
5056 SH_PFC_FUNCTION(pwm1),
5057 SH_PFC_FUNCTION(pwm2),
5058 SH_PFC_FUNCTION(pwm3),
5059 SH_PFC_FUNCTION(pwm4),
5060 SH_PFC_FUNCTION(pwm5),
5061 SH_PFC_FUNCTION(pwm6),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5062 SH_PFC_FUNCTION(qspi0),
5063 SH_PFC_FUNCTION(qspi1),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5064 SH_PFC_FUNCTION(scif0),
5065 SH_PFC_FUNCTION(scif1),
5066 SH_PFC_FUNCTION(scif2),
5067 SH_PFC_FUNCTION(scif3),
5068 SH_PFC_FUNCTION(scif4),
5069 SH_PFC_FUNCTION(scif5),
5070 SH_PFC_FUNCTION(scif_clk),
5071 SH_PFC_FUNCTION(sdhi0),
5072 SH_PFC_FUNCTION(sdhi1),
5073 SH_PFC_FUNCTION(sdhi2),
5074 SH_PFC_FUNCTION(sdhi3),
5075 SH_PFC_FUNCTION(ssi),
5076 SH_PFC_FUNCTION(tmu),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5077 SH_PFC_FUNCTION(tpu),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5078 SH_PFC_FUNCTION(usb0),
5079 SH_PFC_FUNCTION(usb1),
5080 SH_PFC_FUNCTION(usb30),
5081 SH_PFC_FUNCTION(vin4),
5082 SH_PFC_FUNCTION(vin5),
5083 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5084#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5085 .automotive = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5086 SH_PFC_FUNCTION(drif0),
5087 SH_PFC_FUNCTION(drif1),
5088 SH_PFC_FUNCTION(drif2),
5089 SH_PFC_FUNCTION(drif3),
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5090 SH_PFC_FUNCTION(mlb_3pin),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5091 }
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5092#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5093};
5094
5095static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5096#define F_(x, y) FN_##y
5097#define FM(x) FN_##x
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5098 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5099 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5100 1, 1, 1, 1, 1),
5101 GROUP(
5102 /* GP0_31_16 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5103 GP_0_15_FN, GPSR0_15,
5104 GP_0_14_FN, GPSR0_14,
5105 GP_0_13_FN, GPSR0_13,
5106 GP_0_12_FN, GPSR0_12,
5107 GP_0_11_FN, GPSR0_11,
5108 GP_0_10_FN, GPSR0_10,
5109 GP_0_9_FN, GPSR0_9,
5110 GP_0_8_FN, GPSR0_8,
5111 GP_0_7_FN, GPSR0_7,
5112 GP_0_6_FN, GPSR0_6,
5113 GP_0_5_FN, GPSR0_5,
5114 GP_0_4_FN, GPSR0_4,
5115 GP_0_3_FN, GPSR0_3,
5116 GP_0_2_FN, GPSR0_2,
5117 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5118 GP_0_0_FN, GPSR0_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5119 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5120 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5121 0, 0,
5122 0, 0,
5123 0, 0,
5124 GP_1_28_FN, GPSR1_28,
5125 GP_1_27_FN, GPSR1_27,
5126 GP_1_26_FN, GPSR1_26,
5127 GP_1_25_FN, GPSR1_25,
5128 GP_1_24_FN, GPSR1_24,
5129 GP_1_23_FN, GPSR1_23,
5130 GP_1_22_FN, GPSR1_22,
5131 GP_1_21_FN, GPSR1_21,
5132 GP_1_20_FN, GPSR1_20,
5133 GP_1_19_FN, GPSR1_19,
5134 GP_1_18_FN, GPSR1_18,
5135 GP_1_17_FN, GPSR1_17,
5136 GP_1_16_FN, GPSR1_16,
5137 GP_1_15_FN, GPSR1_15,
5138 GP_1_14_FN, GPSR1_14,
5139 GP_1_13_FN, GPSR1_13,
5140 GP_1_12_FN, GPSR1_12,
5141 GP_1_11_FN, GPSR1_11,
5142 GP_1_10_FN, GPSR1_10,
5143 GP_1_9_FN, GPSR1_9,
5144 GP_1_8_FN, GPSR1_8,
5145 GP_1_7_FN, GPSR1_7,
5146 GP_1_6_FN, GPSR1_6,
5147 GP_1_5_FN, GPSR1_5,
5148 GP_1_4_FN, GPSR1_4,
5149 GP_1_3_FN, GPSR1_3,
5150 GP_1_2_FN, GPSR1_2,
5151 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5152 GP_1_0_FN, GPSR1_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5153 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5154 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5155 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5156 1, 1, 1, 1),
5157 GROUP(
5158 /* GP2_31_15 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5159 GP_2_14_FN, GPSR2_14,
5160 GP_2_13_FN, GPSR2_13,
5161 GP_2_12_FN, GPSR2_12,
5162 GP_2_11_FN, GPSR2_11,
5163 GP_2_10_FN, GPSR2_10,
5164 GP_2_9_FN, GPSR2_9,
5165 GP_2_8_FN, GPSR2_8,
5166 GP_2_7_FN, GPSR2_7,
5167 GP_2_6_FN, GPSR2_6,
5168 GP_2_5_FN, GPSR2_5,
5169 GP_2_4_FN, GPSR2_4,
5170 GP_2_3_FN, GPSR2_3,
5171 GP_2_2_FN, GPSR2_2,
5172 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5173 GP_2_0_FN, GPSR2_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5174 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5175 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5176 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5177 1, 1, 1, 1, 1),
5178 GROUP(
5179 /* GP3_31_16 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5180 GP_3_15_FN, GPSR3_15,
5181 GP_3_14_FN, GPSR3_14,
5182 GP_3_13_FN, GPSR3_13,
5183 GP_3_12_FN, GPSR3_12,
5184 GP_3_11_FN, GPSR3_11,
5185 GP_3_10_FN, GPSR3_10,
5186 GP_3_9_FN, GPSR3_9,
5187 GP_3_8_FN, GPSR3_8,
5188 GP_3_7_FN, GPSR3_7,
5189 GP_3_6_FN, GPSR3_6,
5190 GP_3_5_FN, GPSR3_5,
5191 GP_3_4_FN, GPSR3_4,
5192 GP_3_3_FN, GPSR3_3,
5193 GP_3_2_FN, GPSR3_2,
5194 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5195 GP_3_0_FN, GPSR3_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5196 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5197 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5198 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5199 1, 1, 1, 1, 1, 1, 1),
5200 GROUP(
5201 /* GP4_31_18 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5202 GP_4_17_FN, GPSR4_17,
5203 GP_4_16_FN, GPSR4_16,
5204 GP_4_15_FN, GPSR4_15,
5205 GP_4_14_FN, GPSR4_14,
5206 GP_4_13_FN, GPSR4_13,
5207 GP_4_12_FN, GPSR4_12,
5208 GP_4_11_FN, GPSR4_11,
5209 GP_4_10_FN, GPSR4_10,
5210 GP_4_9_FN, GPSR4_9,
5211 GP_4_8_FN, GPSR4_8,
5212 GP_4_7_FN, GPSR4_7,
5213 GP_4_6_FN, GPSR4_6,
5214 GP_4_5_FN, GPSR4_5,
5215 GP_4_4_FN, GPSR4_4,
5216 GP_4_3_FN, GPSR4_3,
5217 GP_4_2_FN, GPSR4_2,
5218 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5219 GP_4_0_FN, GPSR4_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5220 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5221 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5222 0, 0,
5223 0, 0,
5224 0, 0,
5225 0, 0,
5226 0, 0,
5227 0, 0,
5228 GP_5_25_FN, GPSR5_25,
5229 GP_5_24_FN, GPSR5_24,
5230 GP_5_23_FN, GPSR5_23,
5231 GP_5_22_FN, GPSR5_22,
5232 GP_5_21_FN, GPSR5_21,
5233 GP_5_20_FN, GPSR5_20,
5234 GP_5_19_FN, GPSR5_19,
5235 GP_5_18_FN, GPSR5_18,
5236 GP_5_17_FN, GPSR5_17,
5237 GP_5_16_FN, GPSR5_16,
5238 GP_5_15_FN, GPSR5_15,
5239 GP_5_14_FN, GPSR5_14,
5240 GP_5_13_FN, GPSR5_13,
5241 GP_5_12_FN, GPSR5_12,
5242 GP_5_11_FN, GPSR5_11,
5243 GP_5_10_FN, GPSR5_10,
5244 GP_5_9_FN, GPSR5_9,
5245 GP_5_8_FN, GPSR5_8,
5246 GP_5_7_FN, GPSR5_7,
5247 GP_5_6_FN, GPSR5_6,
5248 GP_5_5_FN, GPSR5_5,
5249 GP_5_4_FN, GPSR5_4,
5250 GP_5_3_FN, GPSR5_3,
5251 GP_5_2_FN, GPSR5_2,
5252 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5253 GP_5_0_FN, GPSR5_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5254 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5255 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5256 GP_6_31_FN, GPSR6_31,
5257 GP_6_30_FN, GPSR6_30,
5258 GP_6_29_FN, GPSR6_29,
5259 GP_6_28_FN, GPSR6_28,
5260 GP_6_27_FN, GPSR6_27,
5261 GP_6_26_FN, GPSR6_26,
5262 GP_6_25_FN, GPSR6_25,
5263 GP_6_24_FN, GPSR6_24,
5264 GP_6_23_FN, GPSR6_23,
5265 GP_6_22_FN, GPSR6_22,
5266 GP_6_21_FN, GPSR6_21,
5267 GP_6_20_FN, GPSR6_20,
5268 GP_6_19_FN, GPSR6_19,
5269 GP_6_18_FN, GPSR6_18,
5270 GP_6_17_FN, GPSR6_17,
5271 GP_6_16_FN, GPSR6_16,
5272 GP_6_15_FN, GPSR6_15,
5273 GP_6_14_FN, GPSR6_14,
5274 GP_6_13_FN, GPSR6_13,
5275 GP_6_12_FN, GPSR6_12,
5276 GP_6_11_FN, GPSR6_11,
5277 GP_6_10_FN, GPSR6_10,
5278 GP_6_9_FN, GPSR6_9,
5279 GP_6_8_FN, GPSR6_8,
5280 GP_6_7_FN, GPSR6_7,
5281 GP_6_6_FN, GPSR6_6,
5282 GP_6_5_FN, GPSR6_5,
5283 GP_6_4_FN, GPSR6_4,
5284 GP_6_3_FN, GPSR6_3,
5285 GP_6_2_FN, GPSR6_2,
5286 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5287 GP_6_0_FN, GPSR6_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5288 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5289 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5290 GROUP(-28, 1, 1, 1, 1),
5291 GROUP(
5292 /* GP7_31_4 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5293 GP_7_3_FN, GPSR7_3,
5294 GP_7_2_FN, GPSR7_2,
5295 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5296 GP_7_0_FN, GPSR7_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5297 },
5298#undef F_
5299#undef FM
5300
5301#define F_(x, y) x,
5302#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5303 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5304 IP0_31_28
5305 IP0_27_24
5306 IP0_23_20
5307 IP0_19_16
5308 IP0_15_12
5309 IP0_11_8
5310 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5311 IP0_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5312 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5313 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5314 IP1_31_28
5315 IP1_27_24
5316 IP1_23_20
5317 IP1_19_16
5318 IP1_15_12
5319 IP1_11_8
5320 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5321 IP1_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5322 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5323 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5324 IP2_31_28
5325 IP2_27_24
5326 IP2_23_20
5327 IP2_19_16
5328 IP2_15_12
5329 IP2_11_8
5330 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5331 IP2_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5332 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5333 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5334 IP3_31_28
5335 IP3_27_24
5336 IP3_23_20
5337 IP3_19_16
5338 IP3_15_12
5339 IP3_11_8
5340 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5341 IP3_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5342 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5343 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5344 IP4_31_28
5345 IP4_27_24
5346 IP4_23_20
5347 IP4_19_16
5348 IP4_15_12
5349 IP4_11_8
5350 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5351 IP4_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5352 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5353 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5354 IP5_31_28
5355 IP5_27_24
5356 IP5_23_20
5357 IP5_19_16
5358 IP5_15_12
5359 IP5_11_8
5360 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5361 IP5_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5362 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5363 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5364 IP6_31_28
5365 IP6_27_24
5366 IP6_23_20
5367 IP6_19_16
5368 IP6_15_12
5369 IP6_11_8
5370 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5371 IP6_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5372 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5373 { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5374 GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5375 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5376 IP7_31_28
5377 IP7_27_24
5378 IP7_23_20
5379 IP7_19_16
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5380 /* IP7_15_12 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5381 IP7_11_8
5382 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5383 IP7_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5384 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5385 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5386 IP8_31_28
5387 IP8_27_24
5388 IP8_23_20
5389 IP8_19_16
5390 IP8_15_12
5391 IP8_11_8
5392 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5393 IP8_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5394 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5395 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5396 IP9_31_28
5397 IP9_27_24
5398 IP9_23_20
5399 IP9_19_16
5400 IP9_15_12
5401 IP9_11_8
5402 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5403 IP9_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5404 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5405 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5406 IP10_31_28
5407 IP10_27_24
5408 IP10_23_20
5409 IP10_19_16
5410 IP10_15_12
5411 IP10_11_8
5412 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5413 IP10_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5414 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5415 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5416 IP11_31_28
5417 IP11_27_24
5418 IP11_23_20
5419 IP11_19_16
5420 IP11_15_12
5421 IP11_11_8
5422 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5423 IP11_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5424 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5425 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5426 IP12_31_28
5427 IP12_27_24
5428 IP12_23_20
5429 IP12_19_16
5430 IP12_15_12
5431 IP12_11_8
5432 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5433 IP12_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5434 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5435 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5436 IP13_31_28
5437 IP13_27_24
5438 IP13_23_20
5439 IP13_19_16
5440 IP13_15_12
5441 IP13_11_8
5442 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5443 IP13_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5444 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5445 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5446 IP14_31_28
5447 IP14_27_24
5448 IP14_23_20
5449 IP14_19_16
5450 IP14_15_12
5451 IP14_11_8
5452 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5453 IP14_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5454 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5455 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5456 IP15_31_28
5457 IP15_27_24
5458 IP15_23_20
5459 IP15_19_16
5460 IP15_15_12
5461 IP15_11_8
5462 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5463 IP15_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5464 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5465 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5466 IP16_31_28
5467 IP16_27_24
5468 IP16_23_20
5469 IP16_19_16
5470 IP16_15_12
5471 IP16_11_8
5472 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5473 IP16_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5474 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5475 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5476 IP17_31_28
5477 IP17_27_24
5478 IP17_23_20
5479 IP17_19_16
5480 IP17_15_12
5481 IP17_11_8
5482 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5483 IP17_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5484 },
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5485 { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5486 GROUP(-24, 4, 4),
5487 GROUP(
5488 /* IP18_31_8 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5489 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5490 IP18_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5491 },
5492#undef F_
5493#undef FM
5494
5495#define F_(x, y) x,
5496#define FM(x) FN_##x,
5497 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5498 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5499 1, 1, 1, 2, 2, 1, 2, -3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5500 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5501 MOD_SEL0_31_30_29
5502 MOD_SEL0_28_27
5503 MOD_SEL0_26_25_24
5504 MOD_SEL0_23
5505 MOD_SEL0_22
5506 MOD_SEL0_21
5507 MOD_SEL0_20
5508 MOD_SEL0_19
5509 MOD_SEL0_18_17
5510 MOD_SEL0_16
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5511 /* RESERVED 15 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5512 MOD_SEL0_14_13
5513 MOD_SEL0_12
5514 MOD_SEL0_11
5515 MOD_SEL0_10
5516 MOD_SEL0_9_8
5517 MOD_SEL0_7_6
5518 MOD_SEL0_5
5519 MOD_SEL0_4_3
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5520 /* RESERVED 2, 1, 0 */ ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5521 },
5522 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5523 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5524 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5525 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5526 MOD_SEL1_31_30
5527 MOD_SEL1_29_28_27
5528 MOD_SEL1_26
5529 MOD_SEL1_25_24
5530 MOD_SEL1_23_22_21
5531 MOD_SEL1_20
5532 MOD_SEL1_19
5533 MOD_SEL1_18_17
5534 MOD_SEL1_16
5535 MOD_SEL1_15_14
5536 MOD_SEL1_13
5537 MOD_SEL1_12
5538 MOD_SEL1_11
5539 MOD_SEL1_10
5540 MOD_SEL1_9
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5541 /* RESERVED 8, 7 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5542 MOD_SEL1_6
5543 MOD_SEL1_5
5544 MOD_SEL1_4
5545 MOD_SEL1_3
5546 MOD_SEL1_2
5547 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5548 MOD_SEL1_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5549 },
5550 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5551 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5552 -16, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5553 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5554 MOD_SEL2_31
5555 MOD_SEL2_30
5556 MOD_SEL2_29
5557 MOD_SEL2_28_27
5558 MOD_SEL2_26
5559 MOD_SEL2_25_24_23
5560 MOD_SEL2_22
5561 MOD_SEL2_21
5562 MOD_SEL2_20
5563 MOD_SEL2_19
5564 MOD_SEL2_18
5565 MOD_SEL2_17
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5566 /* RESERVED 16-1 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5567 MOD_SEL2_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5568 },
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]5569 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5570};
5571
5572static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5573 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5574 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5575 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5576 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5577 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5578 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5579 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5580 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5581 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5582 } },
5583 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5584 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5585 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5586 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5587 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5588 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5589 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5590 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5591 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5592 } },
5593 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5594 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5595 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5596 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5597 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5598 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5599 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5600 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5601 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5602 } },
5603 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5604 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5605 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5606 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5607 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5608 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5609 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5610 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5611 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5612 } },
5613 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5614 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5615 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5616 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5617 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5618 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5619 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5620 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5621 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5622 } },
5623 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5624 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5625 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5626 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5627 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5628 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5629 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5630 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5631 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5632 } },
5633 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5634 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5635 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5636 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5637 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5638 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5639 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5640 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5641 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5642 } },
5643 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5644 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5645 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5646 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5647 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5648 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5649 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5650 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5651 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5652 } },
5653 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5654 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5655 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5656 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5657 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5658 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5659 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5660 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5661 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5662 } },
5663 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5664 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5665 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5666 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5667 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5668 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5669 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5670 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5671 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5672 } },
5673 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5674 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5675 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5676 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5677 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5678 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5679 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5680 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5681 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5682 } },
5683 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5684 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5685 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5686 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5687 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5688 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5689 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5690 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5691 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5692 } },
5693 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5694 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5695 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
5696 { PIN_TMS, 4, 2 }, /* TMS */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5697 } },
5698 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5699 { PIN_TDO, 28, 2 }, /* TDO */
5700 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5701 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5702 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5703 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5704 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5705 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5706 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5707 } },
5708 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5709 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5710 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5711 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5712 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5713 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5714 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5715 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5716 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5717 } },
5718 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5719 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5720 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5721 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5722 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5723 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5724 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5725 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5726 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5727 } },
5728 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5729 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5730 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5731 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5732 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5733 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5734 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5735 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5736 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5737 } },
5738 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5739 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5740 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5741 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5742 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5743 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5744 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5745 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5746 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5747 } },
5748 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5749 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5750 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5751 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5752 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5753 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5754 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5755 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5756 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5757 } },
5758 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5759 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5760 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5761 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5762 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5763 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5764 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5765 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5766 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5767 } },
5768 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5769 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5770 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5771 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5772 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5773 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5774 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5775 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5776 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5777 } },
5778 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5779 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5780 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5781 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5782 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5783 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5784 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5785 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5786 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5787 } },
5788 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5789 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5790 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5791 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5792 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5793 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5794 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5795 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5796 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5797 } },
5798 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5799 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5800 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5801 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5802 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5803 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5804 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5805 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5806 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5807 } },
5808 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5809 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5810 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5811 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5812 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5813 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5814 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5815 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5816 } },
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]5817 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5818};
5819
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5820enum ioctrl_regs {
5821 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5822 TDSELCTRL,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5823};
5824
5825static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5826 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5827 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]5828 { /* sentinel */ }
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5829};
5830
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]5831static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5832{
5833 int bit = -EINVAL;
5834
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5835 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5836
5837 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5838 bit = pin & 0x1f;
5839
5840 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5841 bit = (pin & 0x1f) + 12;
5842
5843 return bit;
5844}
5845
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5846static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5847 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5848 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5849 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5850 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5851 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5852 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5853 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5854 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5855 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5856 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5857 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5858 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5859 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5860 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5861 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5862 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5863 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5864 [16] = PIN_AVB_RXC, /* AVB_RXC */
5865 [17] = PIN_AVB_RD0, /* AVB_RD0 */
5866 [18] = PIN_AVB_RD1, /* AVB_RD1 */
5867 [19] = PIN_AVB_RD2, /* AVB_RD2 */
5868 [20] = PIN_AVB_RD3, /* AVB_RD3 */
5869 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5870 [22] = PIN_AVB_TXC, /* AVB_TXC */
5871 [23] = PIN_AVB_TD0, /* AVB_TD0 */
5872 [24] = PIN_AVB_TD1, /* AVB_TD1 */
5873 [25] = PIN_AVB_TD2, /* AVB_TD2 */
5874 [26] = PIN_AVB_TD3, /* AVB_TD3 */
5875 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5876 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5877 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5878 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5879 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5880 } },
5881 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5882 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5883 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5884 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5885 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5886 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5887 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5888 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5889 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5890 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5891 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5892 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5893 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5894 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5895 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5896 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5897 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5898 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5899 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5900 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5901 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5902 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5903 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5904 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5905 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5906 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5907 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5908 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5909 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5910 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5911 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5912 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5913 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5914 } },
5915 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5916 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5917 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5918 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5919 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5920 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5921 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5922 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5923 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5924 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5925 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5926 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5927 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5928 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5929 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5930 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5931 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5932 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5933 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5934 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5935 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5936 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5937 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5938 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5939 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5940 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5941 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5942 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5943 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5944 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5945 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5946 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
5947 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5948 } },
5949 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5950 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
5951 [ 1] = SH_PFC_PIN_NONE,
5952 [ 2] = PIN_FSCLKST, /* FSCLKST */
5953 [ 3] = PIN_EXTALR, /* EXTALR*/
5954 [ 4] = PIN_TRST_N, /* TRST# */
5955 [ 5] = PIN_TCK, /* TCK */
5956 [ 6] = PIN_TMS, /* TMS */
5957 [ 7] = PIN_TDI, /* TDI */
5958 [ 8] = SH_PFC_PIN_NONE,
5959 [ 9] = PIN_ASEBRK, /* ASEBRK */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5960 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5961 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5962 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5963 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5964 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5965 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5966 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5967 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5968 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5969 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5970 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5971 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5972 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5973 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5974 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5975 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5976 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5977 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5978 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5979 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5980 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5981 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5982 } },
5983 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5984 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5985 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5986 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5987 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5988 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5989 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5990 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5991 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5992 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5993 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5994 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5995 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5996 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5997 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5998 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5999 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6000 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6001 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6002 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6003 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6004 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6005 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6006 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6007 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6008 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6009 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6010 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6011 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6012 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6013 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6014 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6015 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6016 } },
6017 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6018 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6019 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6020 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6021 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6022 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6023 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6024 [ 6] = PIN_MLB_REF, /* MLB_REF */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6025 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6026 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6027 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6028 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6029 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6030 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6031 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6032 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6033 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6034 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6035 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6036 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6037 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6038 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6039 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6040 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6041 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6042 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6043 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6044 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6045 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6046 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6047 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6048 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6049 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6050 } },
6051 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6052 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6053 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6054 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6055 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6056 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6057 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6058 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6059 [ 7] = PIN_PRESET_N, /* PRESET# */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6060 [ 8] = SH_PFC_PIN_NONE,
6061 [ 9] = SH_PFC_PIN_NONE,
6062 [10] = SH_PFC_PIN_NONE,
6063 [11] = SH_PFC_PIN_NONE,
6064 [12] = SH_PFC_PIN_NONE,
6065 [13] = SH_PFC_PIN_NONE,
6066 [14] = SH_PFC_PIN_NONE,
6067 [15] = SH_PFC_PIN_NONE,
6068 [16] = SH_PFC_PIN_NONE,
6069 [17] = SH_PFC_PIN_NONE,
6070 [18] = SH_PFC_PIN_NONE,
6071 [19] = SH_PFC_PIN_NONE,
6072 [20] = SH_PFC_PIN_NONE,
6073 [21] = SH_PFC_PIN_NONE,
6074 [22] = SH_PFC_PIN_NONE,
6075 [23] = SH_PFC_PIN_NONE,
6076 [24] = SH_PFC_PIN_NONE,
6077 [25] = SH_PFC_PIN_NONE,
6078 [26] = SH_PFC_PIN_NONE,
6079 [27] = SH_PFC_PIN_NONE,
6080 [28] = SH_PFC_PIN_NONE,
6081 [29] = SH_PFC_PIN_NONE,
6082 [30] = SH_PFC_PIN_NONE,
6083 [31] = SH_PFC_PIN_NONE,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6084 } },
Marek Vasutf2364e12023-09-17 16:08:41 +0200[diff] [blame]6085 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6086};
6087
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6088static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6089 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6090 .get_bias = rcar_pinmux_get_bias,
6091 .set_bias = rcar_pinmux_set_bias,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6092};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6093
6094#ifdef CONFIG_PINCTRL_PFC_R8A774A1
6095const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6096 .name = "r8a774a1_pfc",
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6097 .ops = &r8a7796_pfc_ops,
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6098 .unlock_reg = 0xe6060000, /* PMMR */
6099
6100 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6101
6102 .pins = pinmux_pins,
6103 .nr_pins = ARRAY_SIZE(pinmux_pins),
6104 .groups = pinmux_groups.common,
6105 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6106 .functions = pinmux_functions.common,
6107 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6108
6109 .cfg_regs = pinmux_config_regs,
6110 .drive_regs = pinmux_drive_regs,
6111 .bias_regs = pinmux_bias_regs,
6112 .ioctrl_regs = pinmux_ioctrl_regs,
6113
6114 .pinmux_data = pinmux_data,
6115 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6116};
6117#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6118
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6119#ifdef CONFIG_PINCTRL_PFC_R8A77960
6120const struct sh_pfc_soc_info r8a77960_pinmux_info = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6121 .name = "r8a77960_pfc",
Marek Vasutd0f9c7b2023-01-26 21:01:41 +0100[diff] [blame]6122 .ops = &r8a7796_pfc_ops,
6123 .unlock_reg = 0xe6060000, /* PMMR */
6124
6125 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6126
6127 .pins = pinmux_pins,
6128 .nr_pins = ARRAY_SIZE(pinmux_pins),
6129 .groups = pinmux_groups.common,
6130 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6131 ARRAY_SIZE(pinmux_groups.automotive),
6132 .functions = pinmux_functions.common,
6133 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6134 ARRAY_SIZE(pinmux_functions.automotive),
6135
6136 .cfg_regs = pinmux_config_regs,
6137 .drive_regs = pinmux_drive_regs,
6138 .bias_regs = pinmux_bias_regs,
6139 .ioctrl_regs = pinmux_ioctrl_regs,
6140
6141 .pinmux_data = pinmux_data,
6142 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6143};
6144#endif
6145
6146#ifdef CONFIG_PINCTRL_PFC_R8A77961
6147const struct sh_pfc_soc_info r8a77961_pinmux_info = {
6148 .name = "r8a77961_pfc",
6149 .ops = &r8a7796_pfc_ops,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6150 .unlock_reg = 0xe6060000, /* PMMR */
6151
6152 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6153
6154 .pins = pinmux_pins,
6155 .nr_pins = ARRAY_SIZE(pinmux_pins),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6156 .groups = pinmux_groups.common,
6157 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6158 ARRAY_SIZE(pinmux_groups.automotive),
6159 .functions = pinmux_functions.common,
6160 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6161 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6162
6163 .cfg_regs = pinmux_config_regs,
6164 .drive_regs = pinmux_drive_regs,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6165 .bias_regs = pinmux_bias_regs,
6166 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6167
6168 .pinmux_data = pinmux_data,
6169 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6170};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6171#endif