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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk57b2d802003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053013#include <fs.h>
wdenk525d7b62005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
wdenk4a9cbbe2002-08-27 09:48:53 +000016/* Local functions */
Michal Simeka888af72013-04-26 13:10:07 +020017static int fpga_get_op(char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000018
19/* Local defines */
Michal Simek20d6b952017-01-06 11:20:54 +010020enum {
21 FPGA_NONE = -1,
22 FPGA_INFO,
23 FPGA_LOAD,
24 FPGA_LOADB,
25 FPGA_DUMP,
26 FPGA_LOADMK,
27 FPGA_LOADP,
28 FPGA_LOADBP,
29 FPGA_LOADFS,
30};
wdenk4a9cbbe2002-08-27 09:48:53 +000031
32/* ------------------------------------------------------------------------- */
33/* command form:
34 * fpga <op> <device number> <data addr> <datasize>
35 * where op is 'load', 'dump', or 'info'
36 * If there is no device number field, the fpga environment variable is used.
37 * If there is no data addr field, the fpgadata environment variable is used.
38 * The info command requires no data address field.
39 */
Michal Simeka888af72013-04-26 13:10:07 +020040int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000041{
wdenk1ebf41e2004-01-02 14:00:00 +000042 int op, dev = FPGA_INVALID_DEVICE;
43 size_t data_size = 0;
44 void *fpga_data = NULL;
Simon Glass64b723f2017-08-03 12:22:12 -060045 char *devstr = env_get("fpga");
46 char *datastr = env_get("fpgadata");
wdenk1ebf41e2004-01-02 14:00:00 +000047 int rc = FPGA_FAIL;
Stefano Babic67d7f562010-10-19 09:22:52 +020048 int wrong_parms = 0;
Michal Simeka888af72013-04-26 13:10:07 +020049#if defined(CONFIG_FIT)
Marian Balakowiczd79162d2008-03-12 10:33:01 +010050 const char *fit_uname = NULL;
51 ulong fit_addr;
52#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053053#if defined(CONFIG_CMD_FPGA_LOADFS)
54 fpga_fs_info fpga_fsinfo;
55 fpga_fsinfo.fstype = FS_TYPE_ANY;
56#endif
wdenk4a9cbbe2002-08-27 09:48:53 +000057
wdenk1ebf41e2004-01-02 14:00:00 +000058 if (devstr)
Michal Simeka888af72013-04-26 13:10:07 +020059 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenk1ebf41e2004-01-02 14:00:00 +000060 if (datastr)
Michal Simeka888af72013-04-26 13:10:07 +020061 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +000062
wdenk1ebf41e2004-01-02 14:00:00 +000063 switch (argc) {
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053064#if defined(CONFIG_CMD_FPGA_LOADFS)
65 case 9:
66 fpga_fsinfo.blocksize = (unsigned int)
67 simple_strtoul(argv[5], NULL, 16);
68 fpga_fsinfo.interface = argv[6];
69 fpga_fsinfo.dev_part = argv[7];
70 fpga_fsinfo.filename = argv[8];
71#endif
wdenk1ebf41e2004-01-02 14:00:00 +000072 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simeka888af72013-04-26 13:10:07 +020073 data_size = simple_strtoul(argv[4], NULL, 16);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010074
wdenk1ebf41e2004-01-02 14:00:00 +000075 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczd79162d2008-03-12 10:33:01 +010076#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +020077 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
78 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +010079 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +020080 debug("* fpga: subimage '%s' from FIT image ",
81 fit_uname);
82 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010083 } else
84#endif
85 {
Michal Simeka888af72013-04-26 13:10:07 +020086 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +000087 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simeka888af72013-04-26 13:10:07 +020088 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010089 }
Michal Simek77bb86d2016-01-05 13:51:48 +010090 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010091
wdenk1ebf41e2004-01-02 14:00:00 +000092 case 3: /* fpga <op> <dev | data addr> */
Michal Simeka888af72013-04-26 13:10:07 +020093 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +000094 debug("%s: device = %d\n", __func__, dev);
wdenk1ebf41e2004-01-02 14:00:00 +000095 /* FIXME - this is a really weak test */
Michal Simeka888af72013-04-26 13:10:07 +020096 if ((argc == 3) && (dev > fpga_count())) {
97 /* must be buffer ptr */
Stefano Babicb69b9a52011-12-28 06:47:01 +000098 debug("%s: Assuming buffer pointer in arg 3\n",
Michal Simeka888af72013-04-26 13:10:07 +020099 __func__);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100100
101#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200102 if (fit_parse_subimage(argv[2], (ulong)fpga_data,
103 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100104 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +0200105 debug("* fpga: subimage '%s' from FIT image ",
106 fit_uname);
107 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100108 } else
109#endif
110 {
Michal Simek77bb86d2016-01-05 13:51:48 +0100111 fpga_data = (void *)(uintptr_t)dev;
Michal Simeka888af72013-04-26 13:10:07 +0200112 debug("* fpga: cmdline image addr = 0x%08lx\n",
113 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100114 }
115
Michal Simek77bb86d2016-01-05 13:51:48 +0100116 debug("%s: fpga_data = 0x%lx\n",
117 __func__, (ulong)fpga_data);
wdenk1ebf41e2004-01-02 14:00:00 +0000118 dev = FPGA_INVALID_DEVICE; /* reset device num */
119 }
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100120
wdenk1ebf41e2004-01-02 14:00:00 +0000121 case 2: /* fpga <op> */
Michal Simeka888af72013-04-26 13:10:07 +0200122 op = (int)fpga_get_op(argv[1]);
wdenk1ebf41e2004-01-02 14:00:00 +0000123 break;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100124
wdenk1ebf41e2004-01-02 14:00:00 +0000125 default:
Michal Simeka888af72013-04-26 13:10:07 +0200126 debug("%s: Too many or too few args (%d)\n", __func__, argc);
wdenk1ebf41e2004-01-02 14:00:00 +0000127 op = FPGA_NONE; /* force usage display */
128 break;
129 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000130
Stefano Babic67d7f562010-10-19 09:22:52 +0200131 if (dev == FPGA_INVALID_DEVICE) {
132 puts("FPGA device not specified\n");
133 op = FPGA_NONE;
134 }
135
136 switch (op) {
137 case FPGA_NONE:
138 case FPGA_INFO:
139 break;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530140#if defined(CONFIG_CMD_FPGA_LOADFS)
141 case FPGA_LOADFS:
142 /* Blocksize can be zero */
143 if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
144 !fpga_fsinfo.filename)
145 wrong_parms = 1;
146#endif
Stefano Babic67d7f562010-10-19 09:22:52 +0200147 case FPGA_LOAD:
Michal Simek64c70982014-05-02 13:43:39 +0200148 case FPGA_LOADP:
Stefano Babic67d7f562010-10-19 09:22:52 +0200149 case FPGA_LOADB:
Michal Simek64c70982014-05-02 13:43:39 +0200150 case FPGA_LOADBP:
Stefano Babic67d7f562010-10-19 09:22:52 +0200151 case FPGA_DUMP:
152 if (!fpga_data || !data_size)
153 wrong_parms = 1;
154 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530155#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefano Babic67d7f562010-10-19 09:22:52 +0200156 case FPGA_LOADMK:
157 if (!fpga_data)
158 wrong_parms = 1;
159 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530160#endif
Stefano Babic67d7f562010-10-19 09:22:52 +0200161 }
162
163 if (wrong_parms) {
164 puts("Wrong parameters for FPGA request\n");
165 op = FPGA_NONE;
166 }
167
wdenk1ebf41e2004-01-02 14:00:00 +0000168 switch (op) {
169 case FPGA_NONE:
Simon Glassa06dfc72011-12-10 08:44:01 +0000170 return CMD_RET_USAGE;
wdenk4a9cbbe2002-08-27 09:48:53 +0000171
wdenk1ebf41e2004-01-02 14:00:00 +0000172 case FPGA_INFO:
Michal Simeka888af72013-04-26 13:10:07 +0200173 rc = fpga_info(dev);
wdenk1ebf41e2004-01-02 14:00:00 +0000174 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000175
wdenk1ebf41e2004-01-02 14:00:00 +0000176 case FPGA_LOAD:
Michal Simek14663652014-05-02 14:09:30 +0200177 rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
wdenk1ebf41e2004-01-02 14:00:00 +0000178 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000179
Michal Simek64c70982014-05-02 13:43:39 +0200180#if defined(CONFIG_CMD_FPGA_LOADP)
181 case FPGA_LOADP:
182 rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
183 break;
184#endif
185
wdenk310b4fc2005-01-09 18:12:51 +0000186 case FPGA_LOADB:
Michal Simek14663652014-05-02 14:09:30 +0200187 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
wdenk310b4fc2005-01-09 18:12:51 +0000188 break;
Michal Simek64c70982014-05-02 13:43:39 +0200189
190#if defined(CONFIG_CMD_FPGA_LOADBP)
191 case FPGA_LOADBP:
192 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
193 break;
194#endif
wdenk310b4fc2005-01-09 18:12:51 +0000195
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530196#if defined(CONFIG_CMD_FPGA_LOADFS)
197 case FPGA_LOADFS:
198 rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
199 break;
200#endif
201
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530202#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200203 case FPGA_LOADMK:
Michal Simeka888af72013-04-26 13:10:07 +0200204 switch (genimg_get_format(fpga_data)) {
Heiko Schocher515eb122014-05-28 11:33:33 +0200205#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100206 case IMAGE_FORMAT_LEGACY:
207 {
Michal Simeka888af72013-04-26 13:10:07 +0200208 image_header_t *hdr =
209 (image_header_t *)fpga_data;
210 ulong data;
Michal Simekead2d422013-10-04 10:51:01 +0200211 uint8_t comp;
212
213 comp = image_get_comp(hdr);
214 if (comp == IH_COMP_GZIP) {
Michal Simekbe09b942014-07-16 10:30:50 +0200215#if defined(CONFIG_GZIP)
Michal Simekead2d422013-10-04 10:51:01 +0200216 ulong image_buf = image_get_data(hdr);
217 data = image_get_load(hdr);
218 ulong image_size = ~0UL;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200219
Michal Simekead2d422013-10-04 10:51:01 +0200220 if (gunzip((void *)data, ~0UL,
221 (void *)image_buf,
222 &image_size) != 0) {
223 puts("GUNZIP: error\n");
224 return 1;
225 }
226 data_size = image_size;
Michal Simekbe09b942014-07-16 10:30:50 +0200227#else
228 puts("Gunzip image is not supported\n");
229 return 1;
230#endif
Michal Simekead2d422013-10-04 10:51:01 +0200231 } else {
232 data = (ulong)image_get_data(hdr);
233 data_size = image_get_data_size(hdr);
234 }
Michal Simek14663652014-05-02 14:09:30 +0200235 rc = fpga_load(dev, (void *)data, data_size,
236 BIT_FULL);
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200237 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100238 break;
Heiko Schocher515eb122014-05-28 11:33:33 +0200239#endif
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100240#if defined(CONFIG_FIT)
241 case IMAGE_FORMAT_FIT:
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100242 {
243 const void *fit_hdr = (const void *)fpga_data;
244 int noffset;
Wolfgang Denk74f9b382011-07-30 13:33:49 +0000245 const void *fit_data;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100246
247 if (fit_uname == NULL) {
Michal Simeka888af72013-04-26 13:10:07 +0200248 puts("No FIT subimage unit name\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100249 return 1;
250 }
251
Michal Simeka888af72013-04-26 13:10:07 +0200252 if (!fit_check_format(fit_hdr)) {
253 puts("Bad FIT image format\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100254 return 1;
255 }
256
257 /* get fpga component image node offset */
Michal Simeka888af72013-04-26 13:10:07 +0200258 noffset = fit_image_get_node(fit_hdr,
259 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100260 if (noffset < 0) {
Michal Simeka888af72013-04-26 13:10:07 +0200261 printf("Can't find '%s' FIT subimage\n",
262 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100263 return 1;
264 }
265
266 /* verify integrity */
Simon Glass7428ad12013-05-07 06:11:57 +0000267 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100268 puts ("Bad Data Hash\n");
269 return 1;
270 }
271
272 /* get fpga subimage data address and length */
Michal Simeka888af72013-04-26 13:10:07 +0200273 if (fit_image_get_data(fit_hdr, noffset,
274 &fit_data, &data_size)) {
275 puts("Fpga subimage data not found\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100276 return 1;
277 }
278
Michal Simek14663652014-05-02 14:09:30 +0200279 rc = fpga_load(dev, fit_data, data_size,
280 BIT_FULL);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100281 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100282 break;
283#endif
284 default:
Michal Simeka888af72013-04-26 13:10:07 +0200285 puts("** Unknown image type\n");
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100286 rc = FPGA_FAIL;
287 break;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200288 }
289 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530290#endif
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200291
wdenk1ebf41e2004-01-02 14:00:00 +0000292 case FPGA_DUMP:
Michal Simeka888af72013-04-26 13:10:07 +0200293 rc = fpga_dump(dev, fpga_data, data_size);
wdenk1ebf41e2004-01-02 14:00:00 +0000294 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000295
wdenk1ebf41e2004-01-02 14:00:00 +0000296 default:
Michal Simeka888af72013-04-26 13:10:07 +0200297 printf("Unknown operation\n");
Simon Glassa06dfc72011-12-10 08:44:01 +0000298 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000299 }
Michal Simeka888af72013-04-26 13:10:07 +0200300 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000301}
302
wdenk4a9cbbe2002-08-27 09:48:53 +0000303/*
304 * Map op to supported operations. We don't use a table since we
305 * would just have to relocate it from flash anyway.
306 */
Michal Simeka888af72013-04-26 13:10:07 +0200307static int fpga_get_op(char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000308{
309 int op = FPGA_NONE;
310
Michal Simeka888af72013-04-26 13:10:07 +0200311 if (!strcmp("info", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000312 op = FPGA_INFO;
Michal Simeka888af72013-04-26 13:10:07 +0200313 else if (!strcmp("loadb", opstr))
wdenk310b4fc2005-01-09 18:12:51 +0000314 op = FPGA_LOADB;
Michal Simeka888af72013-04-26 13:10:07 +0200315 else if (!strcmp("load", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000316 op = FPGA_LOAD;
Michal Simek64c70982014-05-02 13:43:39 +0200317#if defined(CONFIG_CMD_FPGA_LOADP)
318 else if (!strcmp("loadp", opstr))
319 op = FPGA_LOADP;
320#endif
321#if defined(CONFIG_CMD_FPGA_LOADBP)
322 else if (!strcmp("loadbp", opstr))
323 op = FPGA_LOADBP;
324#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530325#if defined(CONFIG_CMD_FPGA_LOADFS)
326 else if (!strcmp("loadfs", opstr))
327 op = FPGA_LOADFS;
328#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530329#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200330 else if (!strcmp("loadmk", opstr))
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200331 op = FPGA_LOADMK;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530332#endif
Michal Simeka888af72013-04-26 13:10:07 +0200333 else if (!strcmp("dump", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000334 op = FPGA_DUMP;
wdenk4a9cbbe2002-08-27 09:48:53 +0000335
Michal Simeka888af72013-04-26 13:10:07 +0200336 if (op == FPGA_NONE)
337 printf("Unknown fpga operation \"%s\"\n", opstr);
338
wdenk4a9cbbe2002-08-27 09:48:53 +0000339 return op;
340}
341
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530342#if defined(CONFIG_CMD_FPGA_LOADFS)
343U_BOOT_CMD(fpga, 9, 1, do_fpga,
344#else
Michal Simeka888af72013-04-26 13:10:07 +0200345U_BOOT_CMD(fpga, 6, 1, do_fpga,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530346#endif
Michal Simeka888af72013-04-26 13:10:07 +0200347 "loadable FPGA image support",
348 "[operation type] [device number] [image address] [image size]\n"
349 "fpga operations:\n"
Michal Simek70da5922015-01-26 08:52:27 +0100350 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simeka888af72013-04-26 13:10:07 +0200351 " info\t[dev]\t\t\tlist known device information\n"
352 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek64c70982014-05-02 13:43:39 +0200353#if defined(CONFIG_CMD_FPGA_LOADP)
354 " loadp\t[dev] [address] [size]\t"
355 "Load device from memory buffer with partial bitstream\n"
356#endif
Michal Simeka888af72013-04-26 13:10:07 +0200357 " loadb\t[dev] [address] [size]\t"
358 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek64c70982014-05-02 13:43:39 +0200359#if defined(CONFIG_CMD_FPGA_LOADBP)
360 " loadbp\t[dev] [address] [size]\t"
361 "Load device from bitstream buffer with partial bitstream"
362 "(Xilinx only)\n"
363#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530364#if defined(CONFIG_CMD_FPGA_LOADFS)
365 "Load device from filesystem (FAT by default) (Xilinx only)\n"
366 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
367 " [<dev[:part]>] <filename>\n"
368#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530369#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200370 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100371#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200372 "\n"
373 "\tFor loadmk operating on FIT format uImage address must include\n"
374 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100375#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530376#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100377);