blob: 8add9474ad23c635bcb759624811ed8f4ee81b35 [file] [log] [blame]
Stefan Boschb4bb31d2020-07-10 19:07:37 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2016 Nexell
4 * Hyunseok, Jung <hsjung@nexell.co.kr>
5 */
6
7#include <common.h>
8#include <command.h>
9#include <asm/system.h>
10#include <asm/cache.h>
11#include <asm/sections.h>
12#include <asm/io.h>
13#include <asm/arch/nexell.h>
14#include <asm/arch/clk.h>
15#include <asm/arch/reset.h>
16#include <asm/arch/tieoff.h>
17#include <cpu_func.h>
18#include <linux/delay.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22#ifndef CONFIG_ARCH_CPU_INIT
23#error must be define the macro "CONFIG_ARCH_CPU_INIT"
24#endif
25
26void s_init(void)
27{
28}
29
30static void cpu_soc_init(void)
31{
32 /*
33 * NOTE> ALIVE Power Gate must enable for Alive register access.
34 * must be clear wfi jump address
35 */
36 writel(1, ALIVEPWRGATEREG);
37 writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
38
39 /* write 0xf0 on alive scratchpad reg for boot success check */
40 writel(readl(SCR_SIGNAGURE_READ) | 0xF0, (SCR_SIGNAGURE_SET));
41
42 /* set l2 cache tieoff */
43 nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0, 1);
44 nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
45}
46
47#ifdef CONFIG_PL011_SERIAL
48static void serial_device_init(void)
49{
50 char dev[10];
51 int id;
52
53 sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
54 id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
55
56 struct clk *clk = clk_get((const char *)dev);
57
58 /* reset control: Low active ___|--- */
59 nx_rstcon_setrst(id, RSTCON_ASSERT);
60 udelay(10);
61 nx_rstcon_setrst(id, RSTCON_NEGATE);
62 udelay(10);
63
64 /* set clock */
65 clk_disable(clk);
66 clk_set_rate(clk, CONFIG_PL011_CLOCK);
67 clk_enable(clk);
68}
69#endif
70
71int arch_cpu_init(void)
72{
73 flush_dcache_all();
74 cpu_soc_init();
75 clk_init();
76
77 if (IS_ENABLED(CONFIG_PL011_SERIAL))
78 serial_device_init();
79
80 return 0;
81}
82
83#if defined(CONFIG_DISPLAY_CPUINFO)
84int print_cpuinfo(void)
85{
86 return 0;
87}
88#endif
89
90void reset_cpu(ulong ignored)
91{
92 void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
93 const u32 sw_rst_enb_bitpos = 3;
94 const u32 sw_rst_enb_mask = 1 << sw_rst_enb_bitpos;
95 const u32 sw_rst_bitpos = 12;
96 const u32 sw_rst_mask = 1 << sw_rst_bitpos;
97 int pwrcont = 0x224;
98 int pwrmode = 0x228;
99 u32 read_value;
100
101 read_value = readl((void *)(clkpwr_reg + pwrcont));
102
103 read_value &= ~sw_rst_enb_mask;
104 read_value |= 1 << sw_rst_enb_bitpos;
105
106 writel(read_value, (void *)(clkpwr_reg + pwrcont));
107 writel(sw_rst_mask, (void *)(clkpwr_reg + pwrmode));
108}
109
110void enable_caches(void)
111{
112 /* Enable D-cache. I-cache is already enabled in start.S */
113 dcache_enable();
114}
115
116#if defined(CONFIG_ARCH_MISC_INIT)
117int arch_misc_init(void)
118{
119 return 0;
120}
121#endif /* CONFIG_ARCH_MISC_INIT */