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git01.mediatek.com / filogic / uboot / 57c4aadc696afbbc21c3dd30c1004719f9e5aa07 / . / test / dm / clk.c
blob: 31335a543f176ad49fd4eee78b58cbcb6917cbb9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]2/*
3 * Copyright (C) 2015 Google, Inc
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]4 */
5
6#include <common.h>
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]7#include <clk.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]8#include <dm.h>
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]9#include <asm/clk.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]10#include <dm/test.h>
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]11#include <dm/device-internal.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]12#include <linux/err.h>
13#include <test/ut.h>
14
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]15/* Base test of the clk uclass */
16static int dm_test_clk_base(struct unit_test_state *uts)
17{
18 struct udevice *dev;
19 struct clk clk_method1;
20 struct clk clk_method2;
21
22 /* Get the device using the clk device */
23 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &dev));
24
25 /* Get the same clk port in 2 different ways and compare */
26 ut_assertok(clk_get_by_index(dev, 1, &clk_method1));
27 ut_assertok(clk_get_by_index_nodev(dev_ofnode(dev), 1, &clk_method2));
Sekhar Noricf3119d2019-08-01 19:12:55 +0530[diff] [blame]28 ut_asserteq(clk_is_match(&clk_method1, &clk_method2), true);
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]29 ut_asserteq(clk_method1.id, clk_method2.id);
30
31 return 0;
32}
33
34DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_FDT);
35
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]36static int dm_test_clk(struct unit_test_state *uts)
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]37{
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]38 struct udevice *dev_fixed, *dev_fixed_factor, *dev_clk, *dev_test;
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]39 ulong rate;
40
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]41 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed",
42 &dev_fixed));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]43
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]44 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed-factor",
45 &dev_fixed_factor));
46
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]47 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
48 &dev_clk));
49 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
50 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
51 ut_asserteq(0, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_SPI));
52 ut_asserteq(0, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_I2C));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]53
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]54 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
55 &dev_test));
56 ut_assertok(sandbox_clk_test_get(dev_test));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]57 ut_assertok(sandbox_clk_test_devm_get(dev_test));
Fabrice Gasnier11192712018-07-24 16:31:28 +0200[diff] [blame]58 ut_assertok(sandbox_clk_test_valid(dev_test));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]59
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]60 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
61 SANDBOX_CLK_TEST_ID_DEVM_NULL));
62 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
63 SANDBOX_CLK_TEST_ID_DEVM_NULL,
64 0));
65 ut_asserteq(0, sandbox_clk_test_enable(dev_test,
66 SANDBOX_CLK_TEST_ID_DEVM_NULL));
67 ut_asserteq(0, sandbox_clk_test_disable(dev_test,
68 SANDBOX_CLK_TEST_ID_DEVM_NULL));
69
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]70 ut_asserteq(1234,
71 sandbox_clk_test_get_rate(dev_test,
72 SANDBOX_CLK_TEST_ID_FIXED));
73 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
74 SANDBOX_CLK_TEST_ID_SPI));
75 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
76 SANDBOX_CLK_TEST_ID_I2C));
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200[diff] [blame]77 ut_asserteq(321, sandbox_clk_test_get_rate(dev_test,
78 SANDBOX_CLK_TEST_ID_DEVM1));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]79 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
80 SANDBOX_CLK_TEST_ID_DEVM2));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]81
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]82 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_FIXED,
83 12345);
84 ut_assert(IS_ERR_VALUE(rate));
85 rate = sandbox_clk_test_get_rate(dev_test, SANDBOX_CLK_TEST_ID_FIXED);
86 ut_asserteq(1234, rate);
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]87
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]88 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
89 SANDBOX_CLK_TEST_ID_SPI,
90 1000));
91 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
92 SANDBOX_CLK_TEST_ID_I2C,
93 2000));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]94
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]95 ut_asserteq(1000, sandbox_clk_test_get_rate(dev_test,
96 SANDBOX_CLK_TEST_ID_SPI));
97 ut_asserteq(2000, sandbox_clk_test_get_rate(dev_test,
98 SANDBOX_CLK_TEST_ID_I2C));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]99
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]100 ut_asserteq(1000, sandbox_clk_test_set_rate(dev_test,
101 SANDBOX_CLK_TEST_ID_SPI,
102 10000));
103 ut_asserteq(2000, sandbox_clk_test_set_rate(dev_test,
104 SANDBOX_CLK_TEST_ID_I2C,
105 20000));
106
107 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_SPI, 0);
108 ut_assert(IS_ERR_VALUE(rate));
109 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_I2C, 0);
110 ut_assert(IS_ERR_VALUE(rate));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]111
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]112 ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
113 SANDBOX_CLK_TEST_ID_SPI));
114 ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
115 SANDBOX_CLK_TEST_ID_I2C));
116
117 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
118 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
119 ut_asserteq(10000, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_SPI));
120 ut_asserteq(20000, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_I2C));
121
122 ut_assertok(sandbox_clk_test_enable(dev_test, SANDBOX_CLK_TEST_ID_SPI));
123 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
124 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
125
126 ut_assertok(sandbox_clk_test_enable(dev_test, SANDBOX_CLK_TEST_ID_I2C));
127 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
128 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
129
130 ut_assertok(sandbox_clk_test_disable(dev_test,
131 SANDBOX_CLK_TEST_ID_SPI));
132 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
133 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
134
135 ut_assertok(sandbox_clk_test_disable(dev_test,
136 SANDBOX_CLK_TEST_ID_I2C));
137 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
138 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
139
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]140 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
141 SANDBOX_CLK_ID_SPI));
142 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
143 SANDBOX_CLK_ID_I2C));
144 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
145 SANDBOX_CLK_ID_UART2));
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]146 ut_assertok(sandbox_clk_test_free(dev_test));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]147 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
148 SANDBOX_CLK_ID_SPI));
149 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
150 SANDBOX_CLK_ID_I2C));
151 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
152 SANDBOX_CLK_ID_UART2));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]153
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]154 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
155 SANDBOX_CLK_ID_UART1));
156 ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
157 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
158 SANDBOX_CLK_ID_UART1));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]159 return 0;
160}
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]161DM_TEST(dm_test_clk, DM_TESTF_SCAN_FDT);
Neil Armstrong567a38b2018-04-03 11:44:19 +0200[diff] [blame]162
163static int dm_test_clk_bulk(struct unit_test_state *uts)
164{
165 struct udevice *dev_clk, *dev_test;
166
167 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
168 &dev_clk));
169 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
170 &dev_test));
171 ut_assertok(sandbox_clk_test_get_bulk(dev_test));
172
173 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
174 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
175
176 /* Fixed clock does not support enable, thus should not fail */
177 ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
178 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
179 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
180
181 /* Fixed clock does not support disable, thus should not fail */
182 ut_assertok(sandbox_clk_test_disable_bulk(dev_test));
183 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
184 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
185
186 /* Fixed clock does not support enable, thus should not fail */
187 ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
188 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
189 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
190
191 /* Fixed clock does not support disable, thus should not fail */
192 ut_assertok(sandbox_clk_test_release_bulk(dev_test));
193 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
194 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]195 ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
Neil Armstrong567a38b2018-04-03 11:44:19 +0200[diff] [blame]196
197 return 0;
198}
199DM_TEST(dm_test_clk_bulk, DM_TESTF_SCAN_FDT);