blob: 433b02cceeef069dcdf68318bd76dfcc8050b173 [file] [log] [blame]
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
Marcel Ziswiler9888e122021-10-23 01:15:12 +02006#include "imx8mm-u-boot.dtsi"
7
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +08008/ {
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +08009 firmware {
10 optee {
11 compatible = "linaro,optee-tz";
12 method = "smc";
13 };
14 };
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +020015
16 wdt-reboot {
17 compatible = "wdt-reboot";
18 u-boot,dm-spl;
19 wdt = <&wdog1>;
20 };
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080021};
22
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +020023&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080024 u-boot,dm-spl;
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080025};
26
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +020027&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080028 u-boot,dm-spl;
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080029};
30
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +020031&fec1 {
32 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
33};
34
35&gpio1 {
36 u-boot,dm-spl;
37};
38
39&gpio2 {
40 u-boot,dm-spl;
41};
42
43&gpio3 {
44 u-boot,dm-spl;
45};
46
47&gpio4 {
48 u-boot,dm-spl;
49};
50
51&gpio5 {
52 u-boot,dm-spl;
53};
54
55&i2c1 {
56 u-boot,dm-spl;
57};
58
59&i2c2 {
60 u-boot,dm-spl;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +020061};
62
63&pinctrl_i2c2 {
64 u-boot,dm-spl;
65};
66
67&pinctrl_pmic {
68 u-boot,dm-spl;
69};
70
71&pinctrl_uart3 {
72 u-boot,dm-spl;
73};
74
75&pinctrl_usdhc2 {
76 u-boot,dm-spl;
77};
78
79&pinctrl_usdhc2_gpio {
80 u-boot,dm-spl;
81};
82
83&pinctrl_usdhc3 {
84 u-boot,dm-spl;
85};
86
87&uart3 {
88 u-boot,dm-spl;
89};
90
91&usdhc1 {
92 u-boot,dm-spl;
93};
94
95&usdhc2 {
96 u-boot,dm-spl;
97};
98
99&usdhc3 {
100 u-boot,dm-spl;
101};
102
103&wdog1 {
104 u-boot,dm-spl;
105};