blob: fe45a35d7515a0e979c6cce7e188d877e6ba8593 [file] [log] [blame]
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
6/ {
7 binman: binman {
8 multiple-images;
9 };
10
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080011 firmware {
12 optee {
13 compatible = "linaro,optee-tz";
14 method = "smc";
15 };
16 };
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +020017
18 wdt-reboot {
19 compatible = "wdt-reboot";
20 u-boot,dm-spl;
21 wdt = <&wdog1>;
22 };
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080023};
24
25&{/soc@0} {
26 u-boot,dm-pre-reloc;
27 u-boot,dm-spl;
28};
29
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +020030&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080031 u-boot,dm-spl;
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080032};
33
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +020034&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080035 u-boot,dm-spl;
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080036};
37
38&aips1 {
39 u-boot,dm-spl;
40 u-boot,dm-pre-reloc;
41};
42
43&aips2 {
44 u-boot,dm-spl;
45};
46
47&aips3 {
48 u-boot,dm-spl;
49};
50
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +080051&binman {
52 u-boot-spl-ddr {
53 filename = "u-boot-spl-ddr.bin";
54 pad-byte = <0xff>;
55 align-size = <4>;
56 align = <4>;
57
58 u-boot-spl {
59 align-end = <4>;
60 };
61
62 blob_1: blob-ext@1 {
63 filename = "lpddr4_pmu_train_1d_imem.bin";
64 size = <0x8000>;
65 };
66
67 blob_2: blob-ext@2 {
68 filename = "lpddr4_pmu_train_1d_dmem.bin";
69 size = <0x4000>;
70 };
71
72 blob_3: blob-ext@3 {
73 filename = "lpddr4_pmu_train_2d_imem.bin";
74 size = <0x8000>;
75 };
76
77 blob_4: blob-ext@4 {
78 filename = "lpddr4_pmu_train_2d_dmem.bin";
79 size = <0x4000>;
80 };
81 };
82
83 flash {
84 mkimage {
85 args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
86
87 blob {
88 filename = "u-boot-spl-ddr.bin";
89 };
90 };
91 };
92
93 itb {
94 filename = "u-boot.itb";
95
96 fit {
97 description = "Configuration to load ATF before U-Boot";
98 #address-cells = <1>;
99 fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
100
101 images {
102 uboot {
103 description = "U-Boot (64-bit)";
104 type = "standalone";
105 arch = "arm64";
106 compression = "none";
107 load = <CONFIG_SYS_TEXT_BASE>;
108
109 uboot_blob: blob-ext {
110 filename = "u-boot-nodtb.bin";
111 };
112 };
113
114 atf {
115 description = "ARM Trusted Firmware";
116 type = "firmware";
117 arch = "arm64";
118 compression = "none";
119 load = <0x920000>;
120 entry = <0x920000>;
121
122 atf_blob: blob-ext {
123 filename = "bl31.bin";
124 };
125 };
126
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800127 fdt {
128 description = "NAME";
129 type = "flat_dt";
130 compression = "none";
131
132 uboot_fdt_blob: blob-ext {
133 filename = "u-boot.dtb";
134 };
135 };
136 };
137
138 configurations {
139 default = "conf";
140
141 conf {
142 description = "NAME";
143 firmware = "uboot";
Fabio Estevamc1e26342021-08-23 21:11:09 -0300144 loadables = "atf";
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800145 fdt = "fdt";
146 };
147 };
148 };
149 };
150};
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200151
152&clk {
153 u-boot,dm-spl;
154 u-boot,dm-pre-reloc;
155 /delete-property/ assigned-clocks;
156 /delete-property/ assigned-clock-parents;
157 /delete-property/ assigned-clock-rates;
158};
159
160&fec1 {
161 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
162};
163
164&gpio1 {
165 u-boot,dm-spl;
166};
167
168&gpio2 {
169 u-boot,dm-spl;
170};
171
172&gpio3 {
173 u-boot,dm-spl;
174};
175
176&gpio4 {
177 u-boot,dm-spl;
178};
179
180&gpio5 {
181 u-boot,dm-spl;
182};
183
184&i2c1 {
185 u-boot,dm-spl;
186};
187
188&i2c2 {
189 u-boot,dm-spl;
190};
191
192&iomuxc {
193 u-boot,dm-spl;
194};
195
196&osc_24m {
197 u-boot,dm-spl;
198 u-boot,dm-pre-reloc;
199};
200
201&pinctrl_i2c2 {
202 u-boot,dm-spl;
203};
204
205&pinctrl_pmic {
206 u-boot,dm-spl;
207};
208
209&pinctrl_uart3 {
210 u-boot,dm-spl;
211};
212
213&pinctrl_usdhc2 {
214 u-boot,dm-spl;
215};
216
217&pinctrl_usdhc2_gpio {
218 u-boot,dm-spl;
219};
220
221&pinctrl_usdhc3 {
222 u-boot,dm-spl;
223};
224
225&uart3 {
226 u-boot,dm-spl;
227};
228
229&usdhc1 {
230 u-boot,dm-spl;
231};
232
233&usdhc2 {
234 u-boot,dm-spl;
235};
236
237&usdhc3 {
238 u-boot,dm-spl;
239};
240
241&wdog1 {
242 u-boot,dm-spl;
243};