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wdenk1fe2c702003-03-06 21:55:29 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <s3c2410.h>
30#include <i2c.h>
31
32#include "vcma9.h"
33#include "../common/common_util.h"
34
35/* ------------------------------------------------------------------------- */
36
37#define FCLK_SPEED 1
38
39#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
40#define M_MDIV 0xC3
41#define M_PDIV 0x4
42#define M_SDIV 0x1
43#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
44#define M_MDIV 0xA1
45#define M_PDIV 0x3
46#define M_SDIV 0x1
47#endif
48
49#define USB_CLOCK 1
50
51#if USB_CLOCK==0
52#define U_M_MDIV 0xA1
53#define U_M_PDIV 0x3
54#define U_M_SDIV 0x1
55#elif USB_CLOCK==1
56#define U_M_MDIV 0x48
57#define U_M_PDIV 0x3
58#define U_M_SDIV 0x2
59#endif
60
61static inline void delay(unsigned long loops)
62{
63 __asm__ volatile ("1:\n"
64 "subs %0, %1, #1\n"
65 "bne 1b":"=r" (loops):"0" (loops));
66}
67
68/*
69 * Miscellaneous platform dependent initialisations
70 */
71
72int board_init(void)
73{
74 DECLARE_GLOBAL_DATA_PTR;
wdenk7539dea2003-06-19 23:01:32 +000075 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
76 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
wdenk1fe2c702003-03-06 21:55:29 +000077
78 /* to reduce PLL lock time, adjust the LOCKTIME register */
wdenk7539dea2003-06-19 23:01:32 +000079 clk_power->LOCKTIME = 0xFFFFFF;
wdenk1fe2c702003-03-06 21:55:29 +000080
81 /* configure MPLL */
wdenk7539dea2003-06-19 23:01:32 +000082 clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
wdenk1fe2c702003-03-06 21:55:29 +000083
84 /* some delay between MPLL and UPLL */
85 delay (4000);
86
87 /* configure UPLL */
wdenk7539dea2003-06-19 23:01:32 +000088 clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
wdenk1fe2c702003-03-06 21:55:29 +000089
90 /* some delay between MPLL and UPLL */
91 delay (8000);
92
93 /* set up the I/O ports */
wdenk7539dea2003-06-19 23:01:32 +000094 gpio->GPACON = 0x007FFFFF;
95 gpio->GPBCON = 0x002AAAAA;
96 gpio->GPBUP = 0x000002BF;
97 gpio->GPCCON = 0xAAAAAAAA;
98 gpio->GPCUP = 0x0000FFFF;
99 gpio->GPDCON = 0xAAAAAAAA;
100 gpio->GPDUP = 0x0000FFFF;
101 gpio->GPECON = 0xAAAAAAAA;
102 gpio->GPEUP = 0x000037F7;
103 gpio->GPFCON = 0x00000000;
104 gpio->GPFUP = 0x00000000;
105 gpio->GPGCON = 0xFFEAFF5A;
106 gpio->GPGUP = 0x0000F0DC;
107 gpio->GPHCON = 0x0028AAAA;
108 gpio->GPHUP = 0x00000656;
wdenk1fe2c702003-03-06 21:55:29 +0000109
110 /* setup correct IRQ modes for NIC */
wdenk7539dea2003-06-19 23:01:32 +0000111 gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
112
113 /* select USB port 2 to be host or device (fix to host for now) */
114 gpio->MISCCR |= 0x08;
wdenk1fe2c702003-03-06 21:55:29 +0000115
116 /* init serial */
117 gd->baudrate = CONFIG_BAUDRATE;
118 gd->have_console = 1;
119 serial_init();
120
121 /* arch number of VCMA9-Board */
122 gd->bd->bi_arch_number = 227;
123
124 /* adress of boot parameters */
125 gd->bd->bi_boot_params = 0x30000100;
126
127 icache_enable();
128 dcache_enable();
129
130 return 0;
131}
132
133int dram_init(void)
134{
135 DECLARE_GLOBAL_DATA_PTR;
136
137 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
138 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
139
140 return 0;
141}
wdenk7539dea2003-06-19 23:01:32 +0000142
143/*
144 * NAND flash initialization.
145 */
146#if (CONFIG_COMMANDS & CFG_CMD_NAND)
147extern void
148nand_probe(ulong physadr);
149
150
151static inline void NF_Reset(void)
152{
153 int i;
154
155 NF_SetCE(NFCE_LOW);
156 NF_Cmd(0xFF); /* reset command */
157 for(i = 0; i < 10; i++); /* tWB = 100ns. */
158 NF_WaitRB(); /* wait 200~500us; */
159 NF_SetCE(NFCE_HIGH);
160}
161
162
163static inline void NF_Init(void)
164{
165#define TACLS 0
166#define TWRPH0 3
167#define TWRPH1 0
168 NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
wdenk57b2d802003-06-27 21:31:46 +0000169 /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
170 /* 1 1 1 1, 1 xxx, r xxx, r xxx */
171 /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
wdenk7539dea2003-06-19 23:01:32 +0000172
173 NF_Reset();
174}
175
176void
177nand_init(void)
178{
179 S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
180
181 NF_Init();
182 printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
183 nand_probe((ulong)nand);
184}
185#endif
wdenk1fe2c702003-03-06 21:55:29 +0000186
187/*
188 * Get some Board/PLD Info
189 */
190
191static uchar Get_PLD_ID(void)
192{
193 return(*(volatile uchar *)PLD_ID_REG);
194}
195
196static uchar Get_PLD_BOARD(void)
197{
198 return(*(volatile uchar *)PLD_BOARD_REG);
199}
200
201static uchar Get_PLD_Version(void)
202{
203 return((Get_PLD_ID() >> 4) & 0x0F);
204}
205
206static uchar Get_PLD_Revision(void)
207{
208 return(Get_PLD_ID() & 0x0F);
209}
210
211static int Get_Board_Config(void)
212{
213 uchar config = Get_PLD_BOARD() & 0x03;
214
215 if (config == 3)
216 return 1;
217 else
218 return 0;
219}
220
221static uchar Get_Board_PCB(void)
222{
223 return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
224}
225
226/* ------------------------------------------------------------------------- */
227
228/*
229 * Check Board Identity:
230 */
231
232int checkboard(void)
233{
234 unsigned char s[50];
wdenk1fe2c702003-03-06 21:55:29 +0000235 int i;
236 backup_t *b = (backup_t *) s;
237
238 puts("Board: ");
239
240 i = getenv_r("serial#", s, 32);
241 if ((i < 0) || strncmp (s, "VCMA9", 5)) {
242 get_backup_values (b);
243 if (strncmp (b->signature, "MPL\0", 4) != 0) {
244 puts ("### No HW ID - assuming VCMA9");
245 } else {
246 b->serial_name[5] = 0;
wdenk7539dea2003-06-19 23:01:32 +0000247 printf ("%s-%d PCB Rev %c SN: %s", b->serial_name, Get_Board_Config(),
wdenk1fe2c702003-03-06 21:55:29 +0000248 Get_Board_PCB(), &b->serial_name[6]);
249 }
250 } else {
251 s[5] = 0;
wdenk7539dea2003-06-19 23:01:32 +0000252 printf ("%s-%d PCB Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
wdenk1fe2c702003-03-06 21:55:29 +0000253 &s[6]);
254 }
255 printf("\n");
256 return(0);
257}
258
259
wdenk1fe2c702003-03-06 21:55:29 +0000260void print_vcma9_rev(void)
261{
wdenk7539dea2003-06-19 23:01:32 +0000262 printf("Board: VCMA9-%d PCB Rev: %c (PLD Ver: %d, Rev: %d)\n",
wdenk1fe2c702003-03-06 21:55:29 +0000263 Get_Board_Config(), Get_Board_PCB(),
264 Get_PLD_Version(), Get_PLD_Revision());
265}
266
wdenk7d076412003-05-23 11:38:58 +0000267extern void mem_test_reloc(void);
wdenk1fe2c702003-03-06 21:55:29 +0000268
269int last_stage_init(void)
270{
wdenk7d076412003-05-23 11:38:58 +0000271 mem_test_reloc();
wdenk1fe2c702003-03-06 21:55:29 +0000272 print_vcma9_rev();
273 show_stdio_dev();
274 check_env();
275 return 0;
276}
277
278/***************************************************************************
279 * some helping routines
280 */
281
282int overwrite_console(void)
283{
284 /* return TRUE if console should be overwritten */
285 return 0;
286}
287
288
289/************************************************************************
290* Print VCMA9 Info
291************************************************************************/
292void print_vcma9_info(void)
293{
294 print_vcma9_rev();
295}