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wdenk1fe2c702003-03-06 21:55:29 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <s3c2410.h>
30#include <i2c.h>
31
32#include "vcma9.h"
33#include "../common/common_util.h"
34
35/* ------------------------------------------------------------------------- */
36
37#define FCLK_SPEED 1
38
39#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
40#define M_MDIV 0xC3
41#define M_PDIV 0x4
42#define M_SDIV 0x1
43#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
44#define M_MDIV 0xA1
45#define M_PDIV 0x3
46#define M_SDIV 0x1
47#endif
48
49#define USB_CLOCK 1
50
51#if USB_CLOCK==0
52#define U_M_MDIV 0xA1
53#define U_M_PDIV 0x3
54#define U_M_SDIV 0x1
55#elif USB_CLOCK==1
56#define U_M_MDIV 0x48
57#define U_M_PDIV 0x3
58#define U_M_SDIV 0x2
59#endif
60
61static inline void delay(unsigned long loops)
62{
63 __asm__ volatile ("1:\n"
64 "subs %0, %1, #1\n"
65 "bne 1b":"=r" (loops):"0" (loops));
66}
67
68/*
69 * Miscellaneous platform dependent initialisations
70 */
71
72int board_init(void)
73{
74 DECLARE_GLOBAL_DATA_PTR;
75
76 /* to reduce PLL lock time, adjust the LOCKTIME register */
77 rLOCKTIME = 0xFFFFFF;
78
79 /* configure MPLL */
80 rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
81
82 /* some delay between MPLL and UPLL */
83 delay (4000);
84
85 /* configure UPLL */
86 rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
87
88 /* some delay between MPLL and UPLL */
89 delay (8000);
90
91 /* set up the I/O ports */
92 rGPACON = 0x007FFFFF;
93 rGPBCON = 0x002AAAAA;
94 rGPBUP = 0x000002BF;
95 rGPCCON = 0xAAAAAAAA;
96 rGPCUP = 0x0000FFFF;
97 rGPDCON = 0xAAAAAAAA;
98 rGPDUP = 0x0000FFFF;
99 rGPECON = 0xAAAAAAAA;
100 rGPEUP = 0x000037F7;
101 rGPFCON = 0x00000000;
102 rGPFUP = 0x00000000;
103 rGPGCON = 0xFFEAFF5A;
104 rGPGUP = 0x0000F0DC;
105 rGPHCON = 0x0028AAAA;
106 rGPHUP = 0x00000656;
107
108 /* setup correct IRQ modes for NIC */
109 rEXTINT2 = (rEXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
110
111 /* init serial */
112 gd->baudrate = CONFIG_BAUDRATE;
113 gd->have_console = 1;
114 serial_init();
115
116 /* arch number of VCMA9-Board */
117 gd->bd->bi_arch_number = 227;
118
119 /* adress of boot parameters */
120 gd->bd->bi_boot_params = 0x30000100;
121
122 icache_enable();
123 dcache_enable();
124
125 return 0;
126}
127
128int dram_init(void)
129{
130 DECLARE_GLOBAL_DATA_PTR;
131
132 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
133 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
134
135 return 0;
136}
137
138/*
139 * Get some Board/PLD Info
140 */
141
142static uchar Get_PLD_ID(void)
143{
144 return(*(volatile uchar *)PLD_ID_REG);
145}
146
147static uchar Get_PLD_BOARD(void)
148{
149 return(*(volatile uchar *)PLD_BOARD_REG);
150}
151
152static uchar Get_PLD_Version(void)
153{
154 return((Get_PLD_ID() >> 4) & 0x0F);
155}
156
157static uchar Get_PLD_Revision(void)
158{
159 return(Get_PLD_ID() & 0x0F);
160}
161
162static int Get_Board_Config(void)
163{
164 uchar config = Get_PLD_BOARD() & 0x03;
165
166 if (config == 3)
167 return 1;
168 else
169 return 0;
170}
171
172static uchar Get_Board_PCB(void)
173{
174 return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
175}
176
177/* ------------------------------------------------------------------------- */
178
179/*
180 * Check Board Identity:
181 */
182
183int checkboard(void)
184{
185 unsigned char s[50];
wdenk1fe2c702003-03-06 21:55:29 +0000186 int i;
187 backup_t *b = (backup_t *) s;
188
189 puts("Board: ");
190
191 i = getenv_r("serial#", s, 32);
192 if ((i < 0) || strncmp (s, "VCMA9", 5)) {
193 get_backup_values (b);
194 if (strncmp (b->signature, "MPL\0", 4) != 0) {
195 puts ("### No HW ID - assuming VCMA9");
196 } else {
197 b->serial_name[5] = 0;
198 printf ("%s-%d Rev %c SN: %s", b->serial_name, Get_Board_Config(),
199 Get_Board_PCB(), &b->serial_name[6]);
200 }
201 } else {
202 s[5] = 0;
203 printf ("%s-%d Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
204 &s[6]);
205 }
206 printf("\n");
207 return(0);
208}
209
210
211
212void print_vcma9_rev(void)
213{
214 printf("Board: VCMA9-%d Rev: %c (PLD Ver: %d, Rev: %d)\n",
215 Get_Board_Config(), Get_Board_PCB(),
216 Get_PLD_Version(), Get_PLD_Revision());
217}
218
wdenk7d076412003-05-23 11:38:58 +0000219extern void mem_test_reloc(void);
wdenk1fe2c702003-03-06 21:55:29 +0000220
221int last_stage_init(void)
222{
wdenk7d076412003-05-23 11:38:58 +0000223 mem_test_reloc();
wdenk1fe2c702003-03-06 21:55:29 +0000224 print_vcma9_rev();
225 show_stdio_dev();
226 check_env();
227 return 0;
228}
229
230/***************************************************************************
231 * some helping routines
232 */
233
234int overwrite_console(void)
235{
236 /* return TRUE if console should be overwritten */
237 return 0;
238}
239
240
241/************************************************************************
242* Print VCMA9 Info
243************************************************************************/
244void print_vcma9_info(void)
245{
246 print_vcma9_rev();
247}
248
249