blob: 6b7b8b2e7f7c27e13f521046ea80d8cff2a0f692 [file] [log] [blame]
Dave Liub19ecd32007-09-18 12:37:57 +08001/*
Kim Phillips57a2af32009-07-18 18:42:13 -05002 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
Dave Liub19ecd32007-09-18 12:37:57 +08003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <asm/mmu.h>
14#include <asm/io.h>
15#include <common.h>
16#include <mpc83xx.h>
17#include <pci.h>
18#include <i2c.h>
Anton Vorontsov62842ec2009-01-08 04:26:19 +030019#include <fdt_support.h>
Dave Liub19ecd32007-09-18 12:37:57 +080020#include <asm/fsl_i2c.h>
Anton Vorontsov62842ec2009-01-08 04:26:19 +030021#include <asm/fsl_serdes.h>
Dave Liub19ecd32007-09-18 12:37:57 +080022
Dave Liub19ecd32007-09-18 12:37:57 +080023static struct pci_region pci_regions[] = {
24 {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025 bus_start: CONFIG_SYS_PCI_MEM_BASE,
26 phys_start: CONFIG_SYS_PCI_MEM_PHYS,
27 size: CONFIG_SYS_PCI_MEM_SIZE,
Dave Liub19ecd32007-09-18 12:37:57 +080028 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
29 },
30 {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020031 bus_start: CONFIG_SYS_PCI_MMIO_BASE,
32 phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
33 size: CONFIG_SYS_PCI_MMIO_SIZE,
Dave Liub19ecd32007-09-18 12:37:57 +080034 flags: PCI_REGION_MEM
35 },
36 {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020037 bus_start: CONFIG_SYS_PCI_IO_BASE,
38 phys_start: CONFIG_SYS_PCI_IO_PHYS,
39 size: CONFIG_SYS_PCI_IO_SIZE,
Dave Liub19ecd32007-09-18 12:37:57 +080040 flags: PCI_REGION_IO
41 }
42};
43
Anton Vorontsov62842ec2009-01-08 04:26:19 +030044static struct pci_region pcie_regions_0[] = {
45 {
46 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
47 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
48 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
49 .flags = PCI_REGION_MEM,
50 },
51 {
52 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
53 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
54 .size = CONFIG_SYS_PCIE1_IO_SIZE,
55 .flags = PCI_REGION_IO,
56 },
57};
58
59static struct pci_region pcie_regions_1[] = {
60 {
61 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
62 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
63 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
64 .flags = PCI_REGION_MEM,
65 },
66 {
67 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
68 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
69 .size = CONFIG_SYS_PCIE2_IO_SIZE,
70 .flags = PCI_REGION_IO,
71 },
72};
73
74static int is_pex_x2(void)
75{
76 const char *pex_x2 = getenv("pex_x2");
77
78 if (pex_x2 && !strcmp(pex_x2, "yes"))
79 return 1;
80 return 0;
81}
82
Dave Liub19ecd32007-09-18 12:37:57 +080083void pci_init_board(void)
84{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
Anton Vorontsov62842ec2009-01-08 04:26:19 +030086 volatile sysconf83xx_t *sysconf = &immr->sysconf;
Dave Liub19ecd32007-09-18 12:37:57 +080087 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
88 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
Anton Vorontsov62842ec2009-01-08 04:26:19 +030089 volatile law83xx_t *pcie_law = sysconf->pcielaw;
Dave Liub19ecd32007-09-18 12:37:57 +080090 struct pci_region *reg[] = { pci_regions };
Anton Vorontsov62842ec2009-01-08 04:26:19 +030091 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
92 u32 spridr = in_be32(&immr->sysconf.spridr);
93 int pex2 = is_pex_x2();
Dave Liub19ecd32007-09-18 12:37:57 +080094
Anton Vorontsov30c69922008-10-02 19:17:33 +040095 if (board_pci_host_broken())
Anton Vorontsov62842ec2009-01-08 04:26:19 +030096 goto skip_pci;
Anton Vorontsov30c69922008-10-02 19:17:33 +040097
Dave Liub19ecd32007-09-18 12:37:57 +080098 /* Enable all 5 PCI_CLK_OUTPUTS */
99 clk->occr |= 0xf8000000;
100 udelay(2000);
101
102 /* Configure PCI Local Access Windows */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200103 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
Dave Liub19ecd32007-09-18 12:37:57 +0800104 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
105
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
Dave Liub19ecd32007-09-18 12:37:57 +0800107 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
108
109 udelay(2000);
110
111 mpc83xx_pci_init(1, reg, 0);
Anton Vorontsov62842ec2009-01-08 04:26:19 +0300112skip_pci:
113 /* There is no PEX in MPC8379 parts. */
114 if (PARTID_NO_E(spridr) == SPR_8379)
115 return;
116
Anton Vorontsov58fc0c32009-02-19 18:20:39 +0300117 if (pex2)
118 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
119 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
120 else
121 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
122 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
123
Anton Vorontsov62842ec2009-01-08 04:26:19 +0300124 /* Configure the clock for PCIE controller */
125 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
126 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
127
128 /* Deassert the resets in the control register */
129 out_be32(&sysconf->pecr1, 0xE0008000);
130 if (!pex2)
131 out_be32(&sysconf->pecr2, 0xE0008000);
132 udelay(2000);
133
134 /* Configure PCI Express Local Access Windows */
135 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
136 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
137
138 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
139 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
140
Anton Vorontsov62842ec2009-01-08 04:26:19 +0300141 mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
142}
143
144void ft_pcie_fixup(void *blob, bd_t *bd)
145{
146 const char *status = "disabled (PCIE1 is x2)";
147
148 if (!is_pex_x2())
149 return;
150
151 do_fixup_by_path(blob, "pci2", "status", status,
152 strlen(status) + 1, 1);
Dave Liub19ecd32007-09-18 12:37:57 +0800153}