blob: 29de2e77f01b1ece3d5ba1160745caf1e4ccab32 [file] [log] [blame]
Dave Liub19ecd32007-09-18 12:37:57 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <asm/mmu.h>
14#include <asm/io.h>
15#include <common.h>
16#include <mpc83xx.h>
17#include <pci.h>
18#include <i2c.h>
Anton Vorontsov62842ec2009-01-08 04:26:19 +030019#include <fdt_support.h>
Dave Liub19ecd32007-09-18 12:37:57 +080020#include <asm/fsl_i2c.h>
Anton Vorontsov62842ec2009-01-08 04:26:19 +030021#include <asm/fsl_serdes.h>
Dave Liub19ecd32007-09-18 12:37:57 +080022
23#if defined(CONFIG_PCI)
24static struct pci_region pci_regions[] = {
25 {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020026 bus_start: CONFIG_SYS_PCI_MEM_BASE,
27 phys_start: CONFIG_SYS_PCI_MEM_PHYS,
28 size: CONFIG_SYS_PCI_MEM_SIZE,
Dave Liub19ecd32007-09-18 12:37:57 +080029 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
30 },
31 {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020032 bus_start: CONFIG_SYS_PCI_MMIO_BASE,
33 phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
34 size: CONFIG_SYS_PCI_MMIO_SIZE,
Dave Liub19ecd32007-09-18 12:37:57 +080035 flags: PCI_REGION_MEM
36 },
37 {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038 bus_start: CONFIG_SYS_PCI_IO_BASE,
39 phys_start: CONFIG_SYS_PCI_IO_PHYS,
40 size: CONFIG_SYS_PCI_IO_SIZE,
Dave Liub19ecd32007-09-18 12:37:57 +080041 flags: PCI_REGION_IO
42 }
43};
44
Anton Vorontsov62842ec2009-01-08 04:26:19 +030045static struct pci_region pcie_regions_0[] = {
46 {
47 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
48 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
49 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
50 .flags = PCI_REGION_MEM,
51 },
52 {
53 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
54 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
55 .size = CONFIG_SYS_PCIE1_IO_SIZE,
56 .flags = PCI_REGION_IO,
57 },
58};
59
60static struct pci_region pcie_regions_1[] = {
61 {
62 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
63 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
64 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
65 .flags = PCI_REGION_MEM,
66 },
67 {
68 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
69 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
70 .size = CONFIG_SYS_PCIE2_IO_SIZE,
71 .flags = PCI_REGION_IO,
72 },
73};
74
75static int is_pex_x2(void)
76{
77 const char *pex_x2 = getenv("pex_x2");
78
79 if (pex_x2 && !strcmp(pex_x2, "yes"))
80 return 1;
81 return 0;
82}
83
Dave Liub19ecd32007-09-18 12:37:57 +080084void pci_init_board(void)
85{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
Anton Vorontsov62842ec2009-01-08 04:26:19 +030087 volatile sysconf83xx_t *sysconf = &immr->sysconf;
Dave Liub19ecd32007-09-18 12:37:57 +080088 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
89 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
Anton Vorontsov62842ec2009-01-08 04:26:19 +030090 volatile law83xx_t *pcie_law = sysconf->pcielaw;
Dave Liub19ecd32007-09-18 12:37:57 +080091 struct pci_region *reg[] = { pci_regions };
Anton Vorontsov62842ec2009-01-08 04:26:19 +030092 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
93 u32 spridr = in_be32(&immr->sysconf.spridr);
94 int pex2 = is_pex_x2();
Dave Liub19ecd32007-09-18 12:37:57 +080095
Anton Vorontsov30c69922008-10-02 19:17:33 +040096 if (board_pci_host_broken())
Anton Vorontsov62842ec2009-01-08 04:26:19 +030097 goto skip_pci;
Anton Vorontsov30c69922008-10-02 19:17:33 +040098
Dave Liub19ecd32007-09-18 12:37:57 +080099 /* Enable all 5 PCI_CLK_OUTPUTS */
100 clk->occr |= 0xf8000000;
101 udelay(2000);
102
103 /* Configure PCI Local Access Windows */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
Dave Liub19ecd32007-09-18 12:37:57 +0800105 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
106
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
Dave Liub19ecd32007-09-18 12:37:57 +0800108 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
109
110 udelay(2000);
111
112 mpc83xx_pci_init(1, reg, 0);
Anton Vorontsov62842ec2009-01-08 04:26:19 +0300113skip_pci:
114 /* There is no PEX in MPC8379 parts. */
115 if (PARTID_NO_E(spridr) == SPR_8379)
116 return;
117
Anton Vorontsov58fc0c32009-02-19 18:20:39 +0300118 if (pex2)
119 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
120 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
121 else
122 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
123 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
124
Anton Vorontsov62842ec2009-01-08 04:26:19 +0300125 /* Configure the clock for PCIE controller */
126 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
127 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
128
129 /* Deassert the resets in the control register */
130 out_be32(&sysconf->pecr1, 0xE0008000);
131 if (!pex2)
132 out_be32(&sysconf->pecr2, 0xE0008000);
133 udelay(2000);
134
135 /* Configure PCI Express Local Access Windows */
136 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
137 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
138
139 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
140 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
141
Anton Vorontsov62842ec2009-01-08 04:26:19 +0300142 mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
143}
144
145void ft_pcie_fixup(void *blob, bd_t *bd)
146{
147 const char *status = "disabled (PCIE1 is x2)";
148
149 if (!is_pex_x2())
150 return;
151
152 do_fixup_by_path(blob, "pci2", "status", status,
153 strlen(status) + 1, 1);
Dave Liub19ecd32007-09-18 12:37:57 +0800154}
155#endif /* CONFIG_PCI */