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wdenkc8434db2003-03-26 06:55:25 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
wdenk8dba0502003-03-31 16:34:49 +000026#include <asm/arch/AT91RM9200.h>
Wolfgang Denkbc650fa2005-10-05 01:51:29 +020027#include <at91rm9200_net.h>
28#include <dm9161.h>
wdenkc8434db2003-03-26 06:55:25 +000029
30/* ------------------------------------------------------------------------- */
31/*
32 * Miscelaneous platform dependent initialisations
33 */
34
wdenk381669a2003-06-16 23:50:08 +000035int board_init (void)
36{
37 DECLARE_GLOBAL_DATA_PTR;
38
39 /* Enable Ctrlc */
40 console_init_f ();
41
42 /* Correct IRDA resistor problem */
43 /* Set PA23_TXD in Output */
44 (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2;
wdenkc8434db2003-03-26 06:55:25 +000045
wdenk381669a2003-06-16 23:50:08 +000046 /* memory and cpu-speed are setup before relocation */
47 /* so we do _nothing_ here */
wdenkc8434db2003-03-26 06:55:25 +000048
wdenk381669a2003-06-16 23:50:08 +000049 /* arch number of AT91RM9200DK-Board */
wdenk767fbd42004-10-10 18:41:04 +000050 gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200;
wdenk381669a2003-06-16 23:50:08 +000051 /* adress of boot parameters */
52 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
wdenkc8434db2003-03-26 06:55:25 +000053
wdenk381669a2003-06-16 23:50:08 +000054 return 0;
wdenkc8434db2003-03-26 06:55:25 +000055}
56
wdenk381669a2003-06-16 23:50:08 +000057int dram_init (void)
wdenkc8434db2003-03-26 06:55:25 +000058{
wdenk381669a2003-06-16 23:50:08 +000059 DECLARE_GLOBAL_DATA_PTR;
wdenkc8434db2003-03-26 06:55:25 +000060
wdenk381669a2003-06-16 23:50:08 +000061 gd->bd->bi_dram[0].start = PHYS_SDRAM;
62 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
63 return 0;
wdenkc8434db2003-03-26 06:55:25 +000064}
65
Wolfgang Denkbc650fa2005-10-05 01:51:29 +020066#ifdef CONFIG_DRIVER_ETHER
67#if (CONFIG_COMMANDS & CFG_CMD_NET)
68
69/*
70 * Name:
71 * at91rm9200_GetPhyInterface
72 * Description:
73 * Initialise the interface functions to the PHY
74 * Arguments:
75 * None
76 * Return value:
77 * None
78 */
79void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
80{
81 p_phyops->Init = dm9161_InitPhy;
82 p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
83 p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
84 p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
85}
86
87#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
88#endif /* CONFIG_DRIVER_ETHER */
89
wdenkc8434db2003-03-26 06:55:25 +000090/*
91 * Disk On Chip (NAND) Millenium initialization.
92 * The NAND lives in the CS2* space
93 */
94#if (CONFIG_COMMANDS & CFG_CMD_NAND)
wdenk934c4f82003-09-11 19:48:06 +000095extern ulong nand_probe (ulong physadr);
wdenkc8434db2003-03-26 06:55:25 +000096
wdenk381669a2003-06-16 23:50:08 +000097#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
98void nand_init (void)
wdenkc8434db2003-03-26 06:55:25 +000099{
100 /* Setup Smart Media, fitst enable the address range of CS3 */
wdenk381669a2003-06-16 23:50:08 +0000101 *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
102 /* set the bus interface characteristics based on
103 tDS Data Set up Time 30 - ns
104 tDH Data Hold Time 20 - ns
105 tALS ALE Set up Time 20 - ns
106 16ns at 60 MHz ~= 3 */
wdenkc8434db2003-03-26 06:55:25 +0000107/*memory mapping structures */
108#define SM_ID_RWH (5 << 28)
109#define SM_RWH (1 << 28)
110#define SM_RWS (0 << 24)
111#define SM_TDF (1 << 8)
112#define SM_NWS (3)
wdenk381669a2003-06-16 23:50:08 +0000113 AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
114 AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
115 SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
wdenkc8434db2003-03-26 06:55:25 +0000116
wdenk381669a2003-06-16 23:50:08 +0000117 /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
118 *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
119 AT91C_PC3_BFBAA_SMWE;
120 *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
121 AT91C_PC3_BFBAA_SMWE;
wdenkc8434db2003-03-26 06:55:25 +0000122
123 /* Configure PC2 as input (signal READY of the SmartMedia) */
wdenk381669a2003-06-16 23:50:08 +0000124 *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */
125 *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */
wdenkc8434db2003-03-26 06:55:25 +0000126
127 /* Configure PB1 as input (signal Card Detect of the SmartMedia) */
wdenk381669a2003-06-16 23:50:08 +0000128 *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */
129 *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */
wdenkc8434db2003-03-26 06:55:25 +0000130
wdenk3203c8f2004-07-10 21:45:47 +0000131 /* PIOB and PIOC clock enabling */
132 *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
133 *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
134
wdenk381669a2003-06-16 23:50:08 +0000135 if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
wdenk934c4f82003-09-11 19:48:06 +0000136 printf (" No SmartMedia card inserted\n");
137#ifdef DEBUG
138 printf (" SmartMedia card inserted\n");
wdenkc8434db2003-03-26 06:55:25 +0000139
wdenk381669a2003-06-16 23:50:08 +0000140 printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
wdenk934c4f82003-09-11 19:48:06 +0000141#endif
142 printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
wdenkc8434db2003-03-26 06:55:25 +0000143}
144#endif