blob: 07def18fdcaeef319a168d7deb5f7e5bf766a93d [file] [log] [blame]
wdenkc8434db2003-03-26 06:55:25 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
wdenk8dba0502003-03-31 16:34:49 +000026#include <asm/arch/AT91RM9200.h>
wdenkc8434db2003-03-26 06:55:25 +000027
28/* ------------------------------------------------------------------------- */
29/*
30 * Miscelaneous platform dependent initialisations
31 */
32
33int board_init(void)
34 {
35 DECLARE_GLOBAL_DATA_PTR;
36
37 /* memory and cpu-speed are setup before relocation */
38 /* so we do _nothing_ here */
39
40 /* arch number of AT91RM9200DK-Board */
41 gd->bd->bi_arch_number = 251;
42 /* adress of boot parameters */
43 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
44
45 return 0;
46}
47
48int dram_init(void)
49{
50 DECLARE_GLOBAL_DATA_PTR;
51
52 gd->bd->bi_dram[0].start = PHYS_SDRAM;
53 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
54 return 0;
55}
56
57/*
58 * Disk On Chip (NAND) Millenium initialization.
59 * The NAND lives in the CS2* space
60 */
61#if (CONFIG_COMMANDS & CFG_CMD_NAND)
62extern void
63nand_probe(ulong physadr);
64
65#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
66void
67nand_init(void)
68{
69 /* Setup Smart Media, fitst enable the address range of CS3 */
70 *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
71 /* set the bus interface characteristics based on
72 tDS Data Set up Time 30 - ns
73 tDH Data Hold Time 20 - ns
74 tALS ALE Set up Time 20 - ns
75 16ns at 60 MHz ~= 3 */
76/*memory mapping structures */
77#define SM_ID_RWH (5 << 28)
78#define SM_RWH (1 << 28)
79#define SM_RWS (0 << 24)
80#define SM_TDF (1 << 8)
81#define SM_NWS (3)
82 AT91C_BASE_SMC2->SMC2_CSR[3] = ( SM_RWH|SM_RWS | AT91C_SMC2_ACSS_STANDARD |
83 AT91C_SMC2_DBW_8 | SM_TDF |
84 AT91C_SMC2_WSEN | SM_NWS);
85
86 /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
87 *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
88 *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
89
90 /* Configure PC2 as input (signal READY of the SmartMedia) */
91 *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */
92 *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */
93
94 /* Configure PB1 as input (signal Card Detect of the SmartMedia) */
95 *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */
96 *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */
97
98 if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
99 printf ("No ");
100 printf ("SmartMedia card inserted\n");
101
102 printf("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
103 nand_probe(AT91_SMARTMEDIA_BASE);
104}
105#endif