| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
| 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _RESET_MANAGER_H_ |
| 8 | #define _RESET_MANAGER_H_ |
| 9 | |
| 10 | void reset_cpu(ulong addr); |
| 11 | void reset_deassert_peripherals_handoff(void); |
| 12 | |
| Pavel Machek | 56a00ab | 2014-09-09 14:03:28 +0200 | [diff] [blame^] | 13 | void socfpga_watchdog_reset(void); |
| 14 | |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 15 | struct socfpga_reset_manager { |
| Chin Liang See | 1922dad | 2013-08-07 10:08:03 -0500 | [diff] [blame] | 16 | u32 status; |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 17 | u32 ctrl; |
| Chin Liang See | 1922dad | 2013-08-07 10:08:03 -0500 | [diff] [blame] | 18 | u32 counts; |
| 19 | u32 padding1; |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 20 | u32 mpu_mod_reset; |
| 21 | u32 per_mod_reset; |
| 22 | u32 per2_mod_reset; |
| 23 | u32 brg_mod_reset; |
| 24 | }; |
| 25 | |
| Chin Liang See | 1922dad | 2013-08-07 10:08:03 -0500 | [diff] [blame] | 26 | #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) |
| 27 | #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 |
| 28 | #else |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 29 | #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 |
| Chin Liang See | 1922dad | 2013-08-07 10:08:03 -0500 | [diff] [blame] | 30 | #endif |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 31 | |
| Pavel Machek | 56a00ab | 2014-09-09 14:03:28 +0200 | [diff] [blame^] | 32 | #define RSTMGR_PERMODRST_L4WD0_LSB 6 |
| 33 | |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 34 | #endif /* _RESET_MANAGER_H_ */ |