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git01.mediatek.com / filogic / uboot / 567356a4bea23dabe7069337fe0a08169ffffb39 / . / configs / socfpga_socrates_defconfig
blob: d391f46ee941ed8e5dcf14f2f3546e25c05acef8 [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_ARM=y
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]2CONFIG_ARCH_SOCFPGA=y
Simon Glass2347daa2015-08-19 09:33:42 -0600[diff] [blame]3CONFIG_SYS_MALLOC_F_LEN=0x2000
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]4CONFIG_SPL_DM=y
5CONFIG_DM_GPIO=y
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame^]6CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]7CONFIG_SPL_STACK_R_ADDR=0x00800000
Stefan Roese76ba23f2014-11-07 14:10:41 +0100[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]9CONFIG_SPL=y
Simon Glass2347daa2015-08-19 09:33:42 -0600[diff] [blame]10CONFIG_SPL_STACK_R=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]11# CONFIG_CMD_IMLS is not set
12# CONFIG_CMD_FLASH is not set
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]13CONFIG_CMD_GPIO=y
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame^]14CONFIG_SPL_SIMPLE_BUS=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]15CONFIG_DWAPB_GPIO=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]16CONFIG_SPI_FLASH=y
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]17CONFIG_SPI_FLASH_SPANSION=y
18CONFIG_SPI_FLASH_STMICRO=y
Marek Vasut5ca99542015-07-25 18:47:02 +0200[diff] [blame]19CONFIG_DM_ETH=y
Simon Glass6e378742015-04-05 16:07:34 -0600[diff] [blame]20CONFIG_ETH_DESIGNWARE=y
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]21CONFIG_SYS_NS16550=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]22CONFIG_CADENCE_QSPI=y
23CONFIG_DESIGNWARE_SPI=y