| Masahiro Yamada | d5f8fee | 2015-03-12 13:24:39 +0900 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 2 | CONFIG_ARCH_SOCFPGA=y |
| Simon Glass | 2347daa | 2015-08-19 09:33:42 -0600 | [diff] [blame] | 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 4 | CONFIG_SPL_DM=y |
| 5 | CONFIG_DM_GPIO=y | ||||
| Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 6 | CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y |
| Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 7 | CONFIG_SPL_STACK_R_ADDR=0x00800000 |
| Stefan Roese | 76ba23f | 2014-11-07 14:10:41 +0100 | [diff] [blame] | 8 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" |
| Joe Hershberger | a274ded | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 9 | CONFIG_SPL=y |
| Simon Glass | 2347daa | 2015-08-19 09:33:42 -0600 | [diff] [blame] | 10 | CONFIG_SPL_STACK_R=y |
| Joe Hershberger | 5a9d7f1 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 11 | # CONFIG_CMD_IMLS is not set |
| 12 | # CONFIG_CMD_FLASH is not set | ||||
| Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 13 | CONFIG_CMD_GPIO=y |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 14 | CONFIG_DWAPB_GPIO=y |
| Joe Hershberger | 17491a8 | 2015-06-22 16:15:29 -0500 | [diff] [blame] | 15 | CONFIG_SPI_FLASH=y |
| Marek Vasut | 5ca9954 | 2015-07-25 18:47:02 +0200 | [diff] [blame] | 16 | CONFIG_DM_ETH=y |
| Simon Glass | 6e37874 | 2015-04-05 16:07:34 -0600 | [diff] [blame] | 17 | CONFIG_ETH_DESIGNWARE=y |
| Thomas Chou | a6cec01 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 18 | CONFIG_SYS_NS16550=y |
| Bin Meng | 72a049d | 2015-11-25 05:34:53 -0800 | [diff] [blame^] | 19 | CONFIG_CADENCE_QSPI=y |
| 20 | CONFIG_DESIGNWARE_SPI=y | ||||