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git01.mediatek.com / filogic / uboot / 55b1ebe374a4967ecf6226a0c97a2851ad69bf1c / . / arch / arm / dts / k3-am642-sk-u-boot.dtsi
blob: 3d6be025bd512c4b43d86597a07b2fbdbeb72fea [file] [log] [blame]
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]8/ {
9 chosen {
10 stdout-path = "serial2:115200n8";
11 tick-timer = &timer1;
12 };
Aswath Govindrajua15380e2021-07-26 20:58:03 +0530[diff] [blame]13
14 aliases {
15 mmc1 = &sdhci1;
16 };
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]17
18 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]19 bootph-pre-ram;
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]20 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]21};
22
23&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]25 timer1: timer@2400000 {
26 compatible = "ti,omap5430-timer";
27 reg = <0x0 0x2400000 0x0 0x80>;
28 ti,timer-alwon;
Vignesh Raghavendraf113fce2022-03-11 21:23:22 +0530[diff] [blame]29 clock-frequency = <200000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]31 };
32};
33
34&main_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]36 chipid@14 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]38 };
39};
40
41&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]43 main_i2c0_pins_default: main-i2c0-pins-default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]45 pinctrl-single,pins = <
46 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
47 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
48 >;
49 };
50};
51
52&main_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]54 pinctrl-names = "default";
55 pinctrl-0 = <&main_i2c0_pins_default>;
56 clock-frequency = <400000>;
Neil Armstronga47a3f82022-04-27 13:28:12 +0200[diff] [blame]57
58 tps65219: pmic@30 {
59 compatible = "ti,tps65219";
60 reg = <0x30>;
61
62 regulators {
63 buck1_reg: buck1 {
64 regulator-name = "VDD_CORE";
65 regulator-min-microvolt = <750000>;
66 regulator-max-microvolt = <750000>;
67 regulator-boot-on;
68 regulator-always-on;
69 };
70
71 buck2_reg: buck2 {
72 regulator-name = "VCC1V8";
73 regulator-min-microvolt = <1800000>;
74 regulator-max-microvolt = <1800000>;
75 regulator-boot-on;
76 regulator-always-on;
77 };
78
79 buck3_reg: buck3 {
80 regulator-name = "VDD_LPDDR4";
81 regulator-min-microvolt = <1100000>;
82 regulator-max-microvolt = <1100000>;
83 regulator-boot-on;
84 regulator-always-on;
85 };
86
87 ldo1_reg: ldo1 {
88 regulator-name = "VDDSHV_SD_IO_PMIC";
89 regulator-min-microvolt = <33000000>;
90 regulator-max-microvolt = <33000000>;
91 };
92
93 ldo2_reg: ldo2 {
94 regulator-name = "VDDAR_CORE";
95 regulator-min-microvolt = <850000>;
96 regulator-max-microvolt = <850000>;
97 regulator-boot-on;
98 regulator-always-on;
99 };
100
101 ldo3_reg: ldo3 {
102 regulator-name = "VDDA_1V8";
103 regulator-min-microvolt = <18000000>;
104 regulator-max-microvolt = <18000000>;
105 regulator-boot-on;
106 regulator-always-on;
107 };
108
109 ldo4_reg: ldo4 {
110 regulator-name = "VDD_PHY_2V5";
111 regulator-min-microvolt = <25000000>;
112 regulator-max-microvolt = <25000000>;
113 regulator-boot-on;
114 regulator-always-on;
115 };
116 };
117 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]118};
119
120&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]122};
123
124&dmss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]126};
127
128&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]130};
131
132&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]133 bootph-pre-ram;
Suman Anna91eda102021-05-13 20:10:57 -0500[diff] [blame]134 k3_sysreset: sysreset-controller {
135 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-pre-ram;
Suman Anna91eda102021-05-13 20:10:57 -0500[diff] [blame]137 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]138};
139
140&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]141 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]142};
143
144&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]145 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]146};
147
148&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]149 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]150};
151
152&sdhci0 {
Aswath Govindrajua15380e2021-07-26 20:58:03 +0530[diff] [blame]153 status = "disabled";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]154 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]155};
156
157&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]158 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]159};
160
161&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]162 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]163};
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]164
165&cpsw3g {
166 reg = <0x0 0x8000000 0x0 0x200000>,
167 <0x0 0x43000200 0x0 0x8>;
168 reg-names = "cpsw_nuss", "mac_efuse";
169 /delete-property/ ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]170 bootph-pre-ram;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]171
172 cpsw-phy-sel@04044 {
173 compatible = "ti,am64-phy-gmii-sel";
174 reg = <0x0 0x43004044 0x0 0x8>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]175 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]176 };
177
178 ethernet-ports {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]179 bootph-pre-ram;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]180 };
181};
182
183&cpsw_port2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]184 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]185};
186
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]187&main_bcdma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]188 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]189};
190
191&main_pktdma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]192 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]193};
194
195&rgmii1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]196 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]197};
198
199&rgmii2_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]200 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]201};
202
203&mdio1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]204 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]205};
206
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]207&cpsw3g_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]208 bootph-pre-ram;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]209};
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]210
211&main_usb0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]212 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]213};
214
215&serdes_ln_ctrl {
216 u-boot,mux-autoprobe;
217};
218
219&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]220 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]221};
222
223&usb0 {
224 dr_mode = "host";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]225 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]226};
227
228&serdes_wiz0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]229 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]230};
231
232&serdes0_usb_link {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]233 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]234};
235
236&serdes0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]237 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]238};
239
240&serdes_refclk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]241 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]242};