blob: 7e606cd794ca7b0a2ec1d1abbfc45ae35b84e18d [file] [log] [blame]
Kumar Galae1c09492010-07-15 16:49:03 -05001/*
ramneek mehresh3d339632012-04-18 19:39:53 +00002 * Copyright 2009-2012 Freescale Semiconductor, Inc.
Kumar Galae1c09492010-07-15 16:49:03 -05003 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Galae1c09492010-07-15 16:49:03 -05005 */
6
7/*
8 * Corenet DS style board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include "../board/freescale/common/ics307_clk.h"
14
Shaohui Xie25a2b392011-03-16 10:10:32 +080015#ifdef CONFIG_RAMBOOT_PBL
Aneesh Bansale0f50152015-06-16 10:36:00 +053016#ifdef CONFIG_SECURE_BOOT
Shaohui Xie25a2b392011-03-16 10:10:32 +080017#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Aneesh Bansale0f50152015-06-16 10:36:00 +053019#ifdef CONFIG_NAND
20#define CONFIG_RAMBOOT_NAND
21#endif
Aneesh Bansalb69061d2015-06-16 10:36:43 +053022#define CONFIG_BOOTSCRIPT_COPY_RAM
Aneesh Bansale0f50152015-06-16 10:36:00 +053023#else
24#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
25#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090026#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
York Sun80d89912016-11-18 11:22:17 -080027#if defined(CONFIG_TARGET_P3041DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090028#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
York Sund1bb6022016-11-18 11:26:09 -080029#elif defined(CONFIG_TARGET_P4080DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090030#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
York Sun14bd0742016-11-18 11:32:46 -080031#elif defined(CONFIG_TARGET_P5020DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090032#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
York Suncc85e252016-11-18 11:40:51 -080033#elif defined(CONFIG_TARGET_P5040DS)
Masahiro Yamada8c2c7ec2014-03-11 11:05:16 +090034#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
Shaohui Xieea65fd82012-08-10 02:49:35 +000035#endif
Shaohui Xie25a2b392011-03-16 10:10:32 +080036#endif
Aneesh Bansale0f50152015-06-16 10:36:00 +053037#endif
Shaohui Xie25a2b392011-03-16 10:10:32 +080038
Liu Gangb4611ee2012-08-09 05:10:03 +000039#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
Liu Gang1e084582012-03-08 00:33:18 +000040/* Set 1M boot space */
Liu Gangb4611ee2012-08-09 05:10:03 +000041#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
42#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
Liu Gang1e084582012-03-08 00:33:18 +000044#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Liu Gang1e084582012-03-08 00:33:18 +000045#endif
46
Kumar Galae1c09492010-07-15 16:49:03 -050047/* High Level Configuration Options */
Kumar Galae1c09492010-07-15 16:49:03 -050048#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Kumar Galae1c09492010-07-15 16:49:03 -050049#define CONFIG_MP /* support multiple processors */
50
Kumar Gala51832132010-10-20 16:02:41 -050051#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053052#define CONFIG_SYS_TEXT_BASE 0xeff40000
Kumar Gala51832132010-10-20 16:02:41 -050053#endif
54
Kumar Galae727a362011-01-12 02:48:53 -060055#ifndef CONFIG_RESET_VECTOR_ADDRESS
56#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
57#endif
58
Kumar Galae1c09492010-07-15 16:49:03 -050059#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sunfe845072016-12-28 08:43:45 -080060#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Robert P. J. Daya8099812016-05-03 19:52:49 -040061#define CONFIG_PCIE1 /* PCIE controller 1 */
62#define CONFIG_PCIE2 /* PCIE controller 2 */
Kumar Galae1c09492010-07-15 16:49:03 -050063#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
64#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
Kumar Galae1c09492010-07-15 16:49:03 -050065
Kumar Galae1c09492010-07-15 16:49:03 -050066#define CONFIG_ENV_OVERWRITE
67
Masahiro Yamada8cea9b52017-02-11 22:43:54 +090068#ifndef CONFIG_MTD_NOR_FLASH
Liu Gangb4611ee2012-08-09 05:10:03 +000069#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
Kumar Galae1c09492010-07-15 16:49:03 -050070#define CONFIG_ENV_IS_NOWHERE
Liu Gang85bcd732012-03-08 00:33:20 +000071#endif
Kumar Galae1c09492010-07-15 16:49:03 -050072#else
Kumar Galae1c09492010-07-15 16:49:03 -050073#define CONFIG_FLASH_CFI_DRIVER
74#define CONFIG_SYS_FLASH_CFI
York Sun7b1559d2011-06-30 11:00:56 -070075#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Shaohui Xiec6083892011-05-12 18:46:40 +080076#endif
77
78#if defined(CONFIG_SPIFLASH)
79#define CONFIG_SYS_EXTRA_ENV_RELOC
80#define CONFIG_ENV_IS_IN_SPI_FLASH
81#define CONFIG_ENV_SPI_BUS 0
82#define CONFIG_ENV_SPI_CS 0
83#define CONFIG_ENV_SPI_MAX_HZ 10000000
84#define CONFIG_ENV_SPI_MODE 0
85#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
86#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
87#define CONFIG_ENV_SECT_SIZE 0x10000
88#elif defined(CONFIG_SDCARD)
89#define CONFIG_SYS_EXTRA_ENV_RELOC
90#define CONFIG_ENV_IS_IN_MMC
Fabio Estevamae8c45e2012-01-11 09:20:50 +000091#define CONFIG_FSL_FIXED_MMC_LOCATION
Shaohui Xiec6083892011-05-12 18:46:40 +080092#define CONFIG_SYS_MMC_ENV_DEV 0
93#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053094#define CONFIG_ENV_OFFSET (512 * 1658)
Shaohui Xiee04e16b2011-05-09 16:53:51 +080095#elif defined(CONFIG_NAND)
96#define CONFIG_SYS_EXTRA_ENV_RELOC
97#define CONFIG_ENV_IS_IN_NAND
98#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053099#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gangb4611ee2012-08-09 05:10:03 +0000100#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gang85bcd732012-03-08 00:33:20 +0000101#define CONFIG_ENV_IS_IN_REMOTE
102#define CONFIG_ENV_ADDR 0xffe20000
103#define CONFIG_ENV_SIZE 0x2000
Liu Gang170fae22012-03-08 00:33:15 +0000104#elif defined(CONFIG_ENV_IS_NOWHERE)
105#define CONFIG_ENV_SIZE 0x2000
Shaohui Xiec6083892011-05-12 18:46:40 +0800106#else
107#define CONFIG_ENV_IS_IN_FLASH
Shaohui Xie25a2b392011-03-16 10:10:32 +0800108#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Shaohui Xiec6083892011-05-12 18:46:40 +0800109#define CONFIG_ENV_SIZE 0x2000
110#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Kumar Galae1c09492010-07-15 16:49:03 -0500111#endif
112
113#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
Kumar Galae1c09492010-07-15 16:49:03 -0500114
115/*
116 * These can be toggled for performance analysis, otherwise use default.
117 */
118#define CONFIG_SYS_CACHE_STASHING
119#define CONFIG_BACKSIDE_L2_CACHE
120#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
121#define CONFIG_BTB /* toggle branch predition */
York Sun147fde12011-01-10 12:02:58 +0000122#define CONFIG_DDR_ECC
Kumar Galae1c09492010-07-15 16:49:03 -0500123#ifdef CONFIG_DDR_ECC
124#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
125#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
126#endif
127
128#define CONFIG_ENABLE_36BIT_PHYS
129
130#ifdef CONFIG_PHYS_64BIT
131#define CONFIG_ADDR_MAP
132#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
133#endif
134
York Sun18acc8b2010-09-28 15:20:36 -0700135#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
Kumar Galae1c09492010-07-15 16:49:03 -0500136#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
137#define CONFIG_SYS_MEMTEST_END 0x00400000
138#define CONFIG_SYS_ALT_MEMTEST
139#define CONFIG_PANIC_HANG /* do not reset board on panic */
140
141/*
Shaohui Xie25a2b392011-03-16 10:10:32 +0800142 * Config the L3 Cache as L3 SRAM
143 */
144#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
145#ifdef CONFIG_PHYS_64BIT
146#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
147#else
148#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
149#endif
150#define CONFIG_SYS_L3_SIZE (1024 << 10)
151#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
152
Kumar Galae1c09492010-07-15 16:49:03 -0500153#ifdef CONFIG_PHYS_64BIT
154#define CONFIG_SYS_DCSRBAR 0xf0000000
155#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
156#endif
157
158/* EEPROM */
159#define CONFIG_ID_EEPROM
160#define CONFIG_SYS_I2C_EEPROM_NXID
161#define CONFIG_SYS_EEPROM_BUS_NUM 0
162#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
163#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
164
165/*
166 * DDR Setup
167 */
168#define CONFIG_VERY_BIG_RAM
169#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
170#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
171
172#define CONFIG_DIMM_SLOTS_PER_CTLR 1
york0b2bb6d2010-07-02 22:25:59 +0000173#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
Kumar Galae1c09492010-07-15 16:49:03 -0500174
175#define CONFIG_DDR_SPD
Kumar Galae1c09492010-07-15 16:49:03 -0500176
Kumar Galae1c09492010-07-15 16:49:03 -0500177#define CONFIG_SYS_SPD_BUS_NUM 1
178#define SPD_EEPROM_ADDRESS1 0x51
179#define SPD_EEPROM_ADDRESS2 0x52
Kumar Galae38209e2011-02-09 02:00:08 +0000180#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
York Sun269c7eb2010-10-18 13:46:49 -0700181#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
Kumar Galae1c09492010-07-15 16:49:03 -0500182
183/*
184 * Local Bus Definitions
185 */
186
187/* Set the local bus clock 1/8 of platform clock */
188#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
189
190#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
191#ifdef CONFIG_PHYS_64BIT
192#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
193#else
194#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
195#endif
196
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800197#define CONFIG_SYS_FLASH_BR_PRELIM \
Timur Tabib56570c2012-07-06 07:39:26 +0000198 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800199 | BR_PS_16 | BR_V)
200#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
Kumar Galae1c09492010-07-15 16:49:03 -0500201 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
202
203#define CONFIG_SYS_BR1_PRELIM \
204 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
205#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
206
Kumar Galae1c09492010-07-15 16:49:03 -0500207#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
208#ifdef CONFIG_PHYS_64BIT
209#define PIXIS_BASE_PHYS 0xfffdf0000ull
210#else
211#define PIXIS_BASE_PHYS PIXIS_BASE
212#endif
213
214#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
215#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
216
217#define PIXIS_LBMAP_SWITCH 7
218#define PIXIS_LBMAP_MASK 0xf0
219#define PIXIS_LBMAP_SHIFT 4
220#define PIXIS_LBMAP_ALTBANK 0x40
221
222#define CONFIG_SYS_FLASH_QUIET_TEST
223#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
224
225#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
226#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
227#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
228#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
229
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200230#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kumar Galae1c09492010-07-15 16:49:03 -0500231
Shaohui Xie25a2b392011-03-16 10:10:32 +0800232#if defined(CONFIG_RAMBOOT_PBL)
233#define CONFIG_SYS_RAMBOOT
234#endif
235
Kumar Galae38209e2011-02-09 02:00:08 +0000236/* Nand Flash */
Kumar Galae38209e2011-02-09 02:00:08 +0000237#ifdef CONFIG_NAND_FSL_ELBC
238#define CONFIG_SYS_NAND_BASE 0xffa00000
239#ifdef CONFIG_PHYS_64BIT
240#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
241#else
242#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
243#endif
244
245#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
246#define CONFIG_SYS_MAX_NAND_DEVICE 1
Kumar Galae38209e2011-02-09 02:00:08 +0000247#define CONFIG_CMD_NAND
248#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
249
250/* NAND flash config */
251#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
252 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
253 | BR_PS_8 /* Port Size = 8 bit */ \
254 | BR_MS_FCM /* MSEL = FCM */ \
255 | BR_V) /* valid */
256#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
257 | OR_FCM_PGS /* Large Page*/ \
258 | OR_FCM_CSCT \
259 | OR_FCM_CST \
260 | OR_FCM_CHT \
261 | OR_FCM_SCY_1 \
262 | OR_FCM_TRLX \
263 | OR_FCM_EHTR)
264
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800265#ifdef CONFIG_NAND
266#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
267#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
268#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
269#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
270#else
271#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
272#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
273#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
274#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
275#endif
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800276#else
277#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
278#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
Kumar Galad0af3b92011-08-31 09:50:13 -0500279#endif /* CONFIG_NAND_FSL_ELBC */
Kumar Galae38209e2011-02-09 02:00:08 +0000280
Kumar Galae1c09492010-07-15 16:49:03 -0500281#define CONFIG_SYS_FLASH_EMPTY_INFO
282#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
283#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
284
Kumar Galae1c09492010-07-15 16:49:03 -0500285#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
286#define CONFIG_MISC_INIT_R
287
288#define CONFIG_HWCONFIG
289
290/* define to use L1 as initial stack */
291#define CONFIG_L1_INIT_RAM
292#define CONFIG_SYS_INIT_RAM_LOCK
293#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
294#ifdef CONFIG_PHYS_64BIT
295#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
296#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
297/* The assembler doesn't like typecast */
298#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
299 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
300 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
301#else
302#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
303#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
304#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
305#endif
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200306#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Galae1c09492010-07-15 16:49:03 -0500307
Wolfgang Denk0191e472010-10-26 14:34:52 +0200308#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kumar Galae1c09492010-07-15 16:49:03 -0500309#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
310
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530311#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Kumar Galae1c09492010-07-15 16:49:03 -0500312#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
313
314/* Serial Port - controlled on board with jumper J8
315 * open - index 2
316 * shorted - index 1
317 */
318#define CONFIG_CONS_INDEX 1
Kumar Galae1c09492010-07-15 16:49:03 -0500319#define CONFIG_SYS_NS16550_SERIAL
320#define CONFIG_SYS_NS16550_REG_SIZE 1
321#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
322
323#define CONFIG_SYS_BAUDRATE_TABLE \
324 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
325
326#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
327#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
328#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
329#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
330
Kumar Galae1c09492010-07-15 16:49:03 -0500331/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200332#define CONFIG_SYS_I2C
333#define CONFIG_SYS_I2C_FSL
334#define CONFIG_SYS_FSL_I2C_SPEED 400000
335#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
336#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
337#define CONFIG_SYS_FSL_I2C2_SPEED 400000
338#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
339#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
Kumar Galae1c09492010-07-15 16:49:03 -0500340
341/*
342 * RapidIO
343 */
Kumar Gala8975d7a2010-12-30 12:09:53 -0600344#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500345#ifdef CONFIG_PHYS_64BIT
Kumar Gala8975d7a2010-12-30 12:09:53 -0600346#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500347#else
Kumar Gala8975d7a2010-12-30 12:09:53 -0600348#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500349#endif
Kumar Gala8975d7a2010-12-30 12:09:53 -0600350#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
Kumar Galae1c09492010-07-15 16:49:03 -0500351
Kumar Gala8975d7a2010-12-30 12:09:53 -0600352#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500353#ifdef CONFIG_PHYS_64BIT
Kumar Gala8975d7a2010-12-30 12:09:53 -0600354#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500355#else
Kumar Gala8975d7a2010-12-30 12:09:53 -0600356#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500357#endif
Kumar Gala8975d7a2010-12-30 12:09:53 -0600358#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
Kumar Galae1c09492010-07-15 16:49:03 -0500359
360/*
Liu Gang4cc85322012-03-08 00:33:17 +0000361 * for slave u-boot IMAGE instored in master memory space,
362 * PHYS must be aligned based on the SIZE
363 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800364#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
365#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
366#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
367#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Liu Gang85bcd732012-03-08 00:33:20 +0000368/*
Liu Gangd7b17a92012-08-09 05:09:59 +0000369 * for slave UCODE and ENV instored in master memory space,
Liu Gang85bcd732012-03-08 00:33:20 +0000370 * PHYS must be aligned based on the SIZE
371 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800372#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Liu Gang99e0c292012-08-09 05:10:02 +0000373#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
374#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
Liu Gangd7b17a92012-08-09 05:09:59 +0000375
Liu Gangf420aa92012-03-08 00:33:21 +0000376/* slave core release by master*/
Liu Gang99e0c292012-08-09 05:10:02 +0000377#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
378#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
Liu Gang4cc85322012-03-08 00:33:17 +0000379
380/*
Liu Gangb4611ee2012-08-09 05:10:03 +0000381 * SRIO_PCIE_BOOT - SLAVE
Liu Gang1e084582012-03-08 00:33:18 +0000382 */
Liu Gangb4611ee2012-08-09 05:10:03 +0000383#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
384#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
385#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
386 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
Liu Gang1e084582012-03-08 00:33:18 +0000387#endif
388
389/*
Shaohui Xie58649792011-05-12 18:46:14 +0800390 * eSPI - Enhanced SPI
391 */
Shaohui Xie58649792011-05-12 18:46:14 +0800392#define CONFIG_SF_DEFAULT_SPEED 10000000
393#define CONFIG_SF_DEFAULT_MODE 0
394
395/*
Kumar Galae1c09492010-07-15 16:49:03 -0500396 * General PCI
397 * Memory space is mapped 1-1, but I/O space must start from 0.
398 */
399
400/* controller 1, direct to uli, tgtid 3, Base address 20000 */
401#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
402#ifdef CONFIG_PHYS_64BIT
403#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
404#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
405#else
406#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
407#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
408#endif
409#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
410#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
411#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
412#ifdef CONFIG_PHYS_64BIT
413#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
414#else
415#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
416#endif
417#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
418
419/* controller 2, Slot 2, tgtid 2, Base address 201000 */
420#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
421#ifdef CONFIG_PHYS_64BIT
422#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
423#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
424#else
425#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
426#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
427#endif
428#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
429#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
430#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
431#ifdef CONFIG_PHYS_64BIT
432#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
433#else
434#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
435#endif
436#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
437
438/* controller 3, Slot 1, tgtid 1, Base address 202000 */
Trübenbach, Ralfd8ec2c02011-04-20 13:04:47 +0000439#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500440#ifdef CONFIG_PHYS_64BIT
441#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
442#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
443#else
444#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
445#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
446#endif
447#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
448#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
449#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
450#ifdef CONFIG_PHYS_64BIT
451#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
452#else
453#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
454#endif
455#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
456
Kumar Gala67a6dfe2010-07-09 09:12:18 -0500457/* controller 4, Base address 203000 */
458#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
459#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
460#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
461#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
462#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
463#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
464
Kumar Galae1c09492010-07-15 16:49:03 -0500465/* Qman/Bman */
Haiying Wang325a12f2011-01-20 22:26:31 +0000466#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Kumar Galae1c09492010-07-15 16:49:03 -0500467#define CONFIG_SYS_BMAN_NUM_PORTALS 10
468#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
469#ifdef CONFIG_PHYS_64BIT
470#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
471#else
472#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
473#endif
474#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500475#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
476#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
477#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
478#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
479#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
480 CONFIG_SYS_BMAN_CENA_SIZE)
481#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
482#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Kumar Galae1c09492010-07-15 16:49:03 -0500483#define CONFIG_SYS_QMAN_NUM_PORTALS 10
484#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
485#ifdef CONFIG_PHYS_64BIT
486#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
487#else
488#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
489#endif
490#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500491#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
492#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
493#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
494#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
495#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
496 CONFIG_SYS_QMAN_CENA_SIZE)
497#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
498#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Kumar Galae1c09492010-07-15 16:49:03 -0500499
500#define CONFIG_SYS_DPAA_FMAN
501#define CONFIG_SYS_DPAA_PME
502/* Default address of microcode for the Linux Fman driver */
Timur Tabibb763662011-05-03 13:35:11 -0500503#if defined(CONFIG_SPIFLASH)
504/*
505 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
506 * env, so we got 0x110000.
507 */
Timur Tabi275f4bb2011-11-22 09:21:25 -0600508#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiang83a90842014-03-21 16:21:44 +0800509#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Timur Tabibb763662011-05-03 13:35:11 -0500510#elif defined(CONFIG_SDCARD)
511/*
512 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +0530513 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
514 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Timur Tabibb763662011-05-03 13:35:11 -0500515 */
Timur Tabi275f4bb2011-11-22 09:21:25 -0600516#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiang83a90842014-03-21 16:21:44 +0800517#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
Timur Tabibb763662011-05-03 13:35:11 -0500518#elif defined(CONFIG_NAND)
Timur Tabi275f4bb2011-11-22 09:21:25 -0600519#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Zhao Qiang83a90842014-03-21 16:21:44 +0800520#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gangb4611ee2012-08-09 05:10:03 +0000521#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gang1e084582012-03-08 00:33:18 +0000522/*
523 * Slave has no ucode locally, it can fetch this from remote. When implementing
524 * in two corenet boards, slave's ucode could be stored in master's memory
525 * space, the address can be mapped from slave TLB->slave LAW->
Liu Gangb4611ee2012-08-09 05:10:03 +0000526 * slave SRIO or PCIE outbound window->master inbound window->
527 * master LAW->the ucode address in master's memory space.
Liu Gang1e084582012-03-08 00:33:18 +0000528 */
529#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiang83a90842014-03-21 16:21:44 +0800530#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Kumar Galae1c09492010-07-15 16:49:03 -0500531#else
Timur Tabi275f4bb2011-11-22 09:21:25 -0600532#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiang83a90842014-03-21 16:21:44 +0800533#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Kumar Galae1c09492010-07-15 16:49:03 -0500534#endif
Timur Tabi275f4bb2011-11-22 09:21:25 -0600535#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
536#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
Kumar Galae1c09492010-07-15 16:49:03 -0500537
538#ifdef CONFIG_SYS_DPAA_FMAN
539#define CONFIG_FMAN_ENET
Andy Fleming79ce05b2010-10-20 15:35:16 -0500540#define CONFIG_PHYLIB_10G
541#define CONFIG_PHY_VITESSE
542#define CONFIG_PHY_TERANETICS
Kumar Galae1c09492010-07-15 16:49:03 -0500543#endif
544
545#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000546#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Galae1c09492010-07-15 16:49:03 -0500547
Kumar Galae1c09492010-07-15 16:49:03 -0500548#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Kumar Galae1c09492010-07-15 16:49:03 -0500549#endif /* CONFIG_PCI */
550
551/* SATA */
552#ifdef CONFIG_FSL_SATA_V2
553#define CONFIG_LIBATA
554#define CONFIG_FSL_SATA
555
556#define CONFIG_SYS_SATA_MAX_DEVICE 2
557#define CONFIG_SATA1
558#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
559#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
560#define CONFIG_SATA2
561#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
562#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
563
564#define CONFIG_LBA48
565#define CONFIG_CMD_SATA
Kumar Galae1c09492010-07-15 16:49:03 -0500566#endif
567
568#ifdef CONFIG_FMAN_ENET
569#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
570#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
571#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
572#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
573#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
574
Kumar Galae1c09492010-07-15 16:49:03 -0500575#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
576#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
577#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
578#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
579#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
Kumar Galae1c09492010-07-15 16:49:03 -0500580
581#define CONFIG_SYS_TBIPA_VALUE 8
582#define CONFIG_MII /* MII PHY management */
583#define CONFIG_ETHPRIME "FM1@DTSEC1"
584#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
585#endif
586
587/*
588 * Environment
589 */
Kumar Galae1c09492010-07-15 16:49:03 -0500590#define CONFIG_LOADS_ECHO /* echo on for serial download */
591#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
592
593/*
594 * Command line configuration.
595 */
Kumar Galae1c09492010-07-15 16:49:03 -0500596#define CONFIG_CMD_ERRATA
597#define CONFIG_CMD_IRQ
Kumar Galaaff60ff2011-08-31 09:16:02 -0500598#define CONFIG_CMD_REGINFO
Kumar Galae1c09492010-07-15 16:49:03 -0500599
600#ifdef CONFIG_PCI
601#define CONFIG_CMD_PCI
Kumar Galae1c09492010-07-15 16:49:03 -0500602#endif
603
604/*
605* USB
606*/
ramneek mehresh3d339632012-04-18 19:39:53 +0000607#define CONFIG_HAS_FSL_DR_USB
608#define CONFIG_HAS_FSL_MPH_USB
609
610#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
Kumar Galae1c09492010-07-15 16:49:03 -0500611#define CONFIG_USB_EHCI_FSL
612#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
ramneek mehresh3d339632012-04-18 19:39:53 +0000613#endif
Kumar Galae1c09492010-07-15 16:49:03 -0500614
Kumar Galae1c09492010-07-15 16:49:03 -0500615#ifdef CONFIG_MMC
616#define CONFIG_FSL_ESDHC
617#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
618#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Kumar Galae1c09492010-07-15 16:49:03 -0500619#endif
620
Ruchika Gupta12af67f2014-10-15 11:35:31 +0530621/* Hash command with SHA acceleration supported in hardware */
622#ifdef CONFIG_FSL_CAAM
623#define CONFIG_CMD_HASH
624#define CONFIG_SHA_HW_ACCEL
625#endif
626
Kumar Galae1c09492010-07-15 16:49:03 -0500627/*
628 * Miscellaneous configurable options
629 */
630#define CONFIG_SYS_LONGHELP /* undef to save memory */
631#define CONFIG_CMDLINE_EDITING /* Command-line editing */
632#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
633#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Galae1c09492010-07-15 16:49:03 -0500634#ifdef CONFIG_CMD_KGDB
635#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
636#else
637#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
638#endif
639#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
640#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
641#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Kumar Galae1c09492010-07-15 16:49:03 -0500642
643/*
644 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500645 * have to be in the first 64 MB of memory, since this is
Kumar Galae1c09492010-07-15 16:49:03 -0500646 * the maximum mapped by the Linux kernel during initialization.
647 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500648#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
649#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Galae1c09492010-07-15 16:49:03 -0500650
Kumar Galae1c09492010-07-15 16:49:03 -0500651#ifdef CONFIG_CMD_KGDB
652#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Galae1c09492010-07-15 16:49:03 -0500653#endif
654
655/*
656 * Environment Configuration
657 */
Joe Hershberger257ff782011-10-13 13:03:47 +0000658#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000659#define CONFIG_BOOTFILE "uImage"
Kumar Galae1c09492010-07-15 16:49:03 -0500660#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
661
662/* default location for tftp and bootm */
663#define CONFIG_LOADADDR 1000000
664
York Sund1bb6022016-11-18 11:26:09 -0800665#ifdef CONFIG_TARGET_P4080DS
Ramneek Mehresha0cce272011-06-07 10:10:43 +0000666#define __USB_PHY_TYPE ulpi
667#else
668#define __USB_PHY_TYPE utmi
669#endif
670
Kumar Galae1c09492010-07-15 16:49:03 -0500671#define CONFIG_EXTRA_ENV_SETTINGS \
Emil Medveb250d372010-08-31 22:57:43 -0500672 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
Ramneek Mehresha0cce272011-06-07 10:10:43 +0000673 "bank_intlv=cs0_cs1;" \
ramneek mehresh1b57b002013-09-10 17:37:45 +0530674 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
675 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
Kumar Galae1c09492010-07-15 16:49:03 -0500676 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200677 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
678 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Emil Medveb250d372010-08-31 22:57:43 -0500679 "tftpflash=tftpboot $loadaddr $uboot && " \
680 "protect off $ubootaddr +$filesize && " \
681 "erase $ubootaddr +$filesize && " \
682 "cp.b $loadaddr $ubootaddr $filesize && " \
683 "protect on $ubootaddr +$filesize && " \
684 "cmp.b $loadaddr $ubootaddr $filesize\0" \
Kumar Galae1c09492010-07-15 16:49:03 -0500685 "consoledev=ttyS0\0" \
686 "ramdiskaddr=2000000\0" \
687 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500688 "fdtaddr=1e00000\0" \
Kumar Galae1c09492010-07-15 16:49:03 -0500689 "fdtfile=p4080ds/p4080ds.dtb\0" \
Kim Phillips1dedccc2014-05-14 19:33:45 -0500690 "bdev=sda3\0"
Kumar Galae1c09492010-07-15 16:49:03 -0500691
692#define CONFIG_HDBOOT \
693 "setenv bootargs root=/dev/$bdev rw " \
694 "console=$consoledev,$baudrate $othbootargs;" \
695 "tftp $loadaddr $bootfile;" \
696 "tftp $fdtaddr $fdtfile;" \
697 "bootm $loadaddr - $fdtaddr"
698
699#define CONFIG_NFSBOOTCOMMAND \
700 "setenv bootargs root=/dev/nfs rw " \
701 "nfsroot=$serverip:$rootpath " \
702 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
703 "console=$consoledev,$baudrate $othbootargs;" \
704 "tftp $loadaddr $bootfile;" \
705 "tftp $fdtaddr $fdtfile;" \
706 "bootm $loadaddr - $fdtaddr"
707
708#define CONFIG_RAMBOOTCOMMAND \
709 "setenv bootargs root=/dev/ram rw " \
710 "console=$consoledev,$baudrate $othbootargs;" \
711 "tftp $ramdiskaddr $ramdiskfile;" \
712 "tftp $loadaddr $bootfile;" \
713 "tftp $fdtaddr $fdtfile;" \
714 "bootm $loadaddr $ramdiskaddr $fdtaddr"
715
716#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
717
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000718#include <asm/fsl_secure_boot.h>
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000719
Kumar Galae1c09492010-07-15 16:49:03 -0500720#endif /* __CONFIG_H */