| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pinctrl/qcom,sa8775p-tlmm.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm Technologies, Inc. SA8775P TLMM block |
| 8 | |
| 9 | maintainers: |
| 10 | - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
| 11 | |
| 12 | description: | |
| 13 | Top Level Mode Multiplexer pin controller in Qualcomm SA8775P SoC. |
| 14 | |
| 15 | allOf: |
| 16 | - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# |
| 17 | |
| 18 | properties: |
| 19 | compatible: |
| 20 | const: qcom,sa8775p-tlmm |
| 21 | |
| 22 | reg: |
| 23 | maxItems: 1 |
| 24 | |
| 25 | interrupts: true |
| 26 | interrupt-controller: true |
| 27 | "#interrupt-cells": true |
| 28 | gpio-controller: true |
| 29 | "#gpio-cells": true |
| 30 | gpio-ranges: true |
| 31 | wakeup-parent: true |
| 32 | |
| 33 | gpio-reserved-ranges: |
| 34 | minItems: 1 |
| 35 | maxItems: 74 |
| 36 | |
| 37 | gpio-line-names: |
| 38 | maxItems: 148 |
| 39 | |
| 40 | required: |
| 41 | - compatible |
| 42 | - reg |
| 43 | |
| 44 | additionalProperties: false |
| 45 | |
| 46 | patternProperties: |
| 47 | "-state$": |
| 48 | oneOf: |
| 49 | - $ref: "#/$defs/qcom-sa8775p-tlmm-state" |
| 50 | - patternProperties: |
| 51 | "-pins$": |
| 52 | $ref: "#/$defs/qcom-sa8775p-tlmm-state" |
| 53 | additionalProperties: false |
| 54 | |
| 55 | $defs: |
| 56 | qcom-sa8775p-tlmm-state: |
| 57 | type: object |
| 58 | description: |
| 59 | Pinctrl node's client devices use subnodes for desired pin configuration. |
| 60 | Client device subnodes use below standard properties. |
| 61 | $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state |
| 62 | unevaluatedProperties: false |
| 63 | |
| 64 | properties: |
| 65 | pins: |
| 66 | description: |
| 67 | List of gpio pins affected by the properties specified in this |
| 68 | subnode. |
| 69 | items: |
| 70 | oneOf: |
| 71 | - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-7])$" |
| 72 | - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, ufs_reset ] |
| 73 | minItems: 1 |
| 74 | maxItems: 16 |
| 75 | |
| 76 | function: |
| 77 | description: |
| 78 | Specify the alternative function to be configured for the specified |
| 79 | pins. |
| 80 | |
| 81 | enum: [ atest_char, atest_usb2, audio_ref, cam_mclk, cci_async, cci_i2c, |
| 82 | cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, |
| 83 | cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, |
| 84 | cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, |
| 85 | ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot, |
| 86 | edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot, |
| 87 | edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, |
| 88 | emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0, |
| 89 | emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, |
| 90 | emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, |
| 91 | gcc_gp4, gcc_gp5, gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, |
| 92 | jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3, |
| 93 | mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, |
| 94 | mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, |
| 95 | mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync, |
| 96 | mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, |
| 97 | mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, mi2s_mclk1, |
| 98 | pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, pll_clk, |
| 99 | prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, |
| 100 | qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, |
| 101 | qup0_se5, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, |
| 102 | qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, |
| 103 | qup2_se4, qup2_se5, qup2_se6, qup3_se0, sailss_emac0, |
| 104 | sailss_ospi, sail_top, sgmii_phy, tb_trig, tgu_ch0, tgu_ch1, |
| 105 | tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, tsense_pwm1, tsense_pwm2, |
| 106 | tsense_pwm3, tsense_pwm4, usb2phy_ac, vsense_trigger ] |
| 107 | |
| 108 | required: |
| 109 | - pins |
| 110 | |
| 111 | examples: |
| 112 | - | |
| 113 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 114 | |
| 115 | tlmm: pinctrl@f000000 { |
| 116 | compatible = "qcom,sa8775p-tlmm"; |
| 117 | reg = <0xf000000 0x1000000>; |
| 118 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| 119 | gpio-controller; |
| 120 | #gpio-cells = <2>; |
| 121 | interrupt-controller; |
| 122 | #interrupt-cells = <2>; |
| 123 | gpio-ranges = <&tlmm 0 0 148>; |
| 124 | |
| 125 | qup-uart10-state { |
| 126 | pins = "gpio46", "gpio47"; |
| 127 | function = "qup1_se3"; |
| 128 | }; |
| 129 | }; |
| 130 | ... |