blob: 33c1726f1863ffb5c51595ec7c8e219b93768077 [file] [log] [blame]
Nobuhiro Iwamatsua5413442014-12-02 16:52:20 +09001/*
Nobuhiro Iwamatsu80403952016-04-01 03:51:33 +09002 * board/renesas/rcar-common/common.c
Nobuhiro Iwamatsua5413442014-12-02 16:52:20 +09003 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Nobuhiro Iwamatsu4dc515a2016-04-01 03:51:34 +09006 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsua5413442014-12-02 16:52:20 +09007 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11#include <common.h>
12#include <asm/io.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/arch/rmobile.h>
15#include <asm/arch/rcar-mstp.h>
16
17#define TSTR0 0x04
18#define TSTR0_STR0 0x01
19
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +090020static struct mstp_ctl mstptbl[] = {
21 { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
22 RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
23 { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
24 RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
25 { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
26 RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
27 { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
28 RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
29 { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
30 RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
31 { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
32 RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
Nobuhiro Iwamatsu4dc515a2016-04-01 03:51:34 +090033#ifdef CONFIG_RCAR_GEN3
34 { SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA,
35 RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA },
36#endif
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +090037 { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
38 RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
39 { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
40 RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
41 { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
42 RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
43 { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
44 RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
45 { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
46 RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
47};
48
Nobuhiro Iwamatsua5413442014-12-02 16:52:20 +090049void arch_preboot_os(void)
50{
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +090051 int i;
52
Nobuhiro Iwamatsua5413442014-12-02 16:52:20 +090053 /* stop TMU0 */
54 mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
55
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +090056 /* Stop module clock */
57 for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
Nobuhiro Iwamatsu0181c332016-04-01 03:51:37 +090058 mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr,
59 mstptbl[i].s_dis,
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +090060 mstptbl[i].s_ena);
Nobuhiro Iwamatsu0181c332016-04-01 03:51:37 +090061 mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr,
62 mstptbl[i].r_dis,
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +090063 mstptbl[i].r_ena);
64 }
Nobuhiro Iwamatsua5413442014-12-02 16:52:20 +090065}