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git01.mediatek.com / filogic / uboot / 532d32101c0576871a57cdab85ba2c0a3a82c372 / . / drivers / clk / sunxi / clk_h3.c
blob: 59afba53eef916da244d160cac4d84f939e65fca [file] [log] [blame]
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -0500[diff] [blame]11#include <clk/sunxi.h>
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]12#include <dt-bindings/clock/sun8i-h3-ccu.h>
13#include <dt-bindings/reset/sun8i-h3-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]15
16static struct ccu_clk_gate h3_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]20 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]23 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
24 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
25 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
26 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
27 [CLK_BUS_EHCI3] = GATE(0x060, BIT(27)),
28 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
29 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
30 [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
31 [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
32
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]33 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
34 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
35 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]36 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
37 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
38 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
39 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
40
Jagan Teki755e1812019-02-28 00:26:59 +0530[diff] [blame]41 [CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
42
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]43 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
44 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
45
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]46 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
47 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
48 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
49 [CLK_USB_PHY3] = GATE(0x0cc, BIT(11)),
50 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
51 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
52 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
53 [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)),
54};
55
56static struct ccu_reset h3_resets[] = {
57 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
58 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
59 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
60 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
61
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]62 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
63 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
64 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]65 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]66 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
67 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]68 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
69 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
70 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
71 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(26)),
72 [RST_BUS_EHCI3] = RESET(0x2c0, BIT(27)),
73 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
74 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
75 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
76 [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]77
Jagan Teki755e1812019-02-28 00:26:59 +0530[diff] [blame]78 [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
79
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]80 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
81 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
82 [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]83 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
84 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
85 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
86 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]87};
88
89static const struct ccu_desc h3_ccu_desc = {
90 .gates = h3_gates,
91 .resets = h3_resets,
92};
93
94static int h3_clk_bind(struct udevice *dev)
95{
96 return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
97}
98
99static const struct udevice_id h3_ccu_ids[] = {
100 { .compatible = "allwinner,sun8i-h3-ccu",
101 .data = (ulong)&h3_ccu_desc },
102 { .compatible = "allwinner,sun50i-h5-ccu",
103 .data = (ulong)&h3_ccu_desc },
104 { }
105};
106
107U_BOOT_DRIVER(clk_sun8i_h3) = {
108 .name = "sun8i_h3_ccu",
109 .id = UCLASS_CLK,
110 .of_match = h3_ccu_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]111 .priv_auto = sizeof(struct ccu_priv),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]112 .ops = &sunxi_clk_ops,
113 .probe = sunxi_clk_probe,
114 .bind = h3_clk_bind,
115};