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git01.mediatek.com / filogic / uboot / 755e181a28766c4ce632dac6d5cb8b87858f75fb / . / drivers / clk / sunxi / clk_h3.c
blob: 6111a13f1c176a53519a1c0ffb5fbe3d74e45c0b [file] [log] [blame]
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-h3-ccu.h>
13#include <dt-bindings/reset/sun8i-h3-ccu.h>
14
15static struct ccu_clk_gate h3_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
26 [CLK_BUS_EHCI3] = GATE(0x060, BIT(27)),
27 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
28 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
29 [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
30 [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
31
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]32 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
33 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
34 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
35 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
36
Jagan Teki755e1812019-02-28 00:26:59 +0530[diff] [blame^]37 [CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
38
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]39 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
40 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
41
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]42 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
43 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
44 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
45 [CLK_USB_PHY3] = GATE(0x0cc, BIT(11)),
46 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
47 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
48 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
49 [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)),
50};
51
52static struct ccu_reset h3_resets[] = {
53 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
54 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
55 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
56 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
57
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]58 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
59 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
60 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]61 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]62 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
63 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]64 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
65 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
66 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
67 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(26)),
68 [RST_BUS_EHCI3] = RESET(0x2c0, BIT(27)),
69 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
70 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
71 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
72 [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]73
Jagan Teki755e1812019-02-28 00:26:59 +0530[diff] [blame^]74 [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
75
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]76 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
77 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
78 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
79 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
Jagan Teki2ee11ff2018-08-02 15:43:02 +0530[diff] [blame]80};
81
82static const struct ccu_desc h3_ccu_desc = {
83 .gates = h3_gates,
84 .resets = h3_resets,
85};
86
87static int h3_clk_bind(struct udevice *dev)
88{
89 return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
90}
91
92static const struct udevice_id h3_ccu_ids[] = {
93 { .compatible = "allwinner,sun8i-h3-ccu",
94 .data = (ulong)&h3_ccu_desc },
95 { .compatible = "allwinner,sun50i-h5-ccu",
96 .data = (ulong)&h3_ccu_desc },
97 { }
98};
99
100U_BOOT_DRIVER(clk_sun8i_h3) = {
101 .name = "sun8i_h3_ccu",
102 .id = UCLASS_CLK,
103 .of_match = h3_ccu_ids,
104 .priv_auto_alloc_size = sizeof(struct ccu_priv),
105 .ops = &sunxi_clk_ops,
106 .probe = sunxi_clk_probe,
107 .bind = h3_clk_bind,
108};