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Patrice Chotard5c121e12017-09-13 18:00:07 +02001/*
2 * This header provides constants for the STM32H7 RCC IP
3 */
4
5#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H
6#define _DT_BINDINGS_MFD_STM32H7_RCC_H
7
8/* AHB3 */
9#define STM32H7_RCC_AHB3_MDMA 0
10#define STM32H7_RCC_AHB3_DMA2D 4
11#define STM32H7_RCC_AHB3_JPGDEC 5
12#define STM32H7_RCC_AHB3_FMC 12
13#define STM32H7_RCC_AHB3_QUADSPI 14
14#define STM32H7_RCC_AHB3_SDMMC1 16
Patrick Delaunay8c6e6132019-11-06 16:16:33 +010015#define STM32H7_RCC_AHB3_CPU 31
Patrice Chotard5c121e12017-09-13 18:00:07 +020016#define STM32H7_RCC_AHB3_CPU1 31
17
18#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
19
20/* AHB1 */
21#define STM32H7_RCC_AHB1_DMA1 0
22#define STM32H7_RCC_AHB1_DMA2 1
23#define STM32H7_RCC_AHB1_ADC12 5
24#define STM32H7_RCC_AHB1_ART 14
25#define STM32H7_RCC_AHB1_ETH1MAC 15
26#define STM32H7_RCC_AHB1_USB1OTG 25
27#define STM32H7_RCC_AHB1_USB2OTG 27
28#define STM32H7_RCC_AHB1_CPU2 31
29
30#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
31
32/* AHB2 */
33#define STM32H7_RCC_AHB2_CAMITF 0
34#define STM32H7_RCC_AHB2_CRYPT 4
35#define STM32H7_RCC_AHB2_HASH 5
36#define STM32H7_RCC_AHB2_RNG 6
37#define STM32H7_RCC_AHB2_SDMMC2 9
38
39#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
40
41/* AHB4 */
42#define STM32H7_RCC_AHB4_GPIOA 0
43#define STM32H7_RCC_AHB4_GPIOB 1
44#define STM32H7_RCC_AHB4_GPIOC 2
45#define STM32H7_RCC_AHB4_GPIOD 3
46#define STM32H7_RCC_AHB4_GPIOE 4
47#define STM32H7_RCC_AHB4_GPIOF 5
48#define STM32H7_RCC_AHB4_GPIOG 6
49#define STM32H7_RCC_AHB4_GPIOH 7
50#define STM32H7_RCC_AHB4_GPIOI 8
51#define STM32H7_RCC_AHB4_GPIOJ 9
52#define STM32H7_RCC_AHB4_GPIOK 10
53#define STM32H7_RCC_AHB4_CRC 19
54#define STM32H7_RCC_AHB4_BDMA 21
55#define STM32H7_RCC_AHB4_ADC3 24
56#define STM32H7_RCC_AHB4_HSEM 25
57
58#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
59
Patrice Chotard5c121e12017-09-13 18:00:07 +020060/* APB3 */
61#define STM32H7_RCC_APB3_LTDC 3
62#define STM32H7_RCC_APB3_DSI 4
63
64#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))
65
66/* APB1L */
67#define STM32H7_RCC_APB1L_TIM2 0
68#define STM32H7_RCC_APB1L_TIM3 1
69#define STM32H7_RCC_APB1L_TIM4 2
70#define STM32H7_RCC_APB1L_TIM5 3
71#define STM32H7_RCC_APB1L_TIM6 4
72#define STM32H7_RCC_APB1L_TIM7 5
73#define STM32H7_RCC_APB1L_TIM12 6
74#define STM32H7_RCC_APB1L_TIM13 7
75#define STM32H7_RCC_APB1L_TIM14 8
76#define STM32H7_RCC_APB1L_LPTIM1 9
77#define STM32H7_RCC_APB1L_SPI2 14
78#define STM32H7_RCC_APB1L_SPI3 15
79#define STM32H7_RCC_APB1L_SPDIF_RX 16
80#define STM32H7_RCC_APB1L_USART2 17
81#define STM32H7_RCC_APB1L_USART3 18
82#define STM32H7_RCC_APB1L_UART4 19
83#define STM32H7_RCC_APB1L_UART5 20
84#define STM32H7_RCC_APB1L_I2C1 21
85#define STM32H7_RCC_APB1L_I2C2 22
86#define STM32H7_RCC_APB1L_I2C3 23
87#define STM32H7_RCC_APB1L_HDMICEC 27
88#define STM32H7_RCC_APB1L_DAC12 29
89#define STM32H7_RCC_APB1L_USART7 30
90#define STM32H7_RCC_APB1L_USART8 31
91
92#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))
93
94/* APB1H */
95#define STM32H7_RCC_APB1H_CRS 1
96#define STM32H7_RCC_APB1H_SWP 2
97#define STM32H7_RCC_APB1H_OPAMP 4
98#define STM32H7_RCC_APB1H_MDIOS 5
99#define STM32H7_RCC_APB1H_FDCAN 8
100
101#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))
102
103/* APB2 */
104#define STM32H7_RCC_APB2_TIM1 0
105#define STM32H7_RCC_APB2_TIM8 1
106#define STM32H7_RCC_APB2_USART1 4
107#define STM32H7_RCC_APB2_USART6 5
108#define STM32H7_RCC_APB2_SPI1 12
109#define STM32H7_RCC_APB2_SPI4 13
110#define STM32H7_RCC_APB2_TIM15 16
111#define STM32H7_RCC_APB2_TIM16 17
112#define STM32H7_RCC_APB2_TIM17 18
113#define STM32H7_RCC_APB2_SPI5 20
114#define STM32H7_RCC_APB2_SAI1 22
115#define STM32H7_RCC_APB2_SAI2 23
116#define STM32H7_RCC_APB2_SAI3 24
117#define STM32H7_RCC_APB2_DFSDM1 28
118#define STM32H7_RCC_APB2_HRTIM 29
119
120#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))
121
122/* APB4 */
123#define STM32H7_RCC_APB4_SYSCFG 1
124#define STM32H7_RCC_APB4_LPUART1 3
125#define STM32H7_RCC_APB4_SPI6 5
126#define STM32H7_RCC_APB4_I2C4 7
127#define STM32H7_RCC_APB4_LPTIM2 9
128#define STM32H7_RCC_APB4_LPTIM3 10
129#define STM32H7_RCC_APB4_LPTIM4 11
130#define STM32H7_RCC_APB4_LPTIM5 12
131#define STM32H7_RCC_APB4_COMP12 14
132#define STM32H7_RCC_APB4_VREF 15
133#define STM32H7_RCC_APB4_SAI4 21
134#define STM32H7_RCC_APB4_TMPSENS 26
135
136#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))
137
138#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */