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git01.mediatek.com / filogic / uboot / 51e7778ad9737d7e6a1f71148caaad0e2f7eca1c / . / board / amcc / yucca / init.S
blob: c63002b8afc53a76b5b2c04472b9738c5d3416ef [file] [log] [blame]
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1/*
Stefan Roese511b61d2007-03-08 10:10:18 +0100[diff] [blame]2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]25
26#include <ppc_asm.tmpl>
27#include <config.h>
Peter Tyser133c0fe2010-04-12 22:28:07 -0500[diff] [blame]28#include <asm/mmu.h>
Stefan Roese3ddce572010-09-20 16:05:31 +0200[diff] [blame]29#include <asm/ppc4xx.h>
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]30
31/**************************************************************************
32 * TLB TABLE
33 *
34 * This table is used by the cpu boot code to setup the initial tlb
35 * entries. Rather than make broad assumptions in the cpu source tree,
36 * this table lets each board set things up however they like.
37 *
38 * Pointer to the table is returned in r1
39 *
40 *************************************************************************/
41
42 .section .bootpg,"ax"
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]43
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]44/**************************************************************************
45 * TLB table for revA
46 *************************************************************************/
47 .globl tlbtabA
48tlbtabA:
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]49 tlbtab_start
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]50
Stefan Roese511b61d2007-03-08 10:10:18 +0100[diff] [blame]51 /*
52 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
53 * speed up boot process. It is patched after relocation to enable SA_I
54 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]55 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
Stefan Roese511b61d2007-03-08 10:10:18 +0100[diff] [blame]56
57 /*
58 * TLB entries for SDRAM are not needed on this platform.
59 * They are dynamically generated in the SPD DDR(2) detection
60 * routine.
61 */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]62
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]63 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
64 tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]65
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]66 tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
67 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]68
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]69 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
70 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
71 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
72 tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]73
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]74 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
75 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
76 tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
77 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
78 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
79 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]80 tlbtab_end
81
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]82/**************************************************************************
83 * TLB table for revB
84 *
Wolfgang Denkb8474132006-08-10 15:40:49 +0200[diff] [blame]85 * Notice: revB of the 440SPe chip is very strict about PLB real addresses
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]86 * and ranges to be mapped for config space: it seems to only work with
87 * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
88 * set otherwise) while revA uses c_nnnn_nnnn.
89 *************************************************************************/
90 .globl tlbtabB
91tlbtabB:
92 tlbtab_start
Stefan Roese511b61d2007-03-08 10:10:18 +0100[diff] [blame]93
94 /*
95 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
96 * speed up boot process. It is patched after relocation to enable SA_I
97 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]98 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]99
Stefan Roese511b61d2007-03-08 10:10:18 +0100[diff] [blame]100 /*
101 * TLB entries for SDRAM are not needed on this platform.
102 * They are dynamically generated in the SPD DDR(2) detection
103 * routine.
104 */
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]105
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]106 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
107 tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]108
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]109 tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
110 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]111
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]112 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
113 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
114 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]115
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]116 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
117 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
118 tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
119 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
120 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
121 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]122 tlbtab_end