blob: 3e0c96c5055616e44c9511d496ae1bd2f61a6593 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simekc8cf4712014-02-05 08:06:29 +01002/*
3 * Copyright (c) 2004-2008 Texas Instruments
4 *
5 * (C) Copyright 2002
6 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
Michal Simekc8cf4712014-02-05 08:06:29 +01007 */
8
9OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
10OUTPUT_ARCH(arm)
11ENTRY(_start)
12SECTIONS
13{
14 . = 0x00000000;
15
16 . = ALIGN(4);
Ilias Apalodimascdb58392024-03-15 08:43:50 +020017 __image_copy_start = ADDR(.text);
Michal Simekc8cf4712014-02-05 08:06:29 +010018 .text :
19 {
Masahiro Yamada22ea4152014-06-05 19:47:45 +090020 *(.vectors)
Michal Simekc8cf4712014-02-05 08:06:29 +010021 CPUDIR/start.o (.text*)
Alexander Graf94a10f22018-06-12 07:48:37 +020022 }
23
24 /* This needs to come before *(.text*) */
Ilias Apalodimas772acf82024-03-15 08:43:51 +020025 .efi_runtime : {
Ilias Apalodimas048a9ec2024-03-15 08:43:49 +020026 __efi_runtime_start = .;
Alexander Graf94a10f22018-06-12 07:48:37 +020027 *(.text.efi_runtime*)
28 *(.rodata.efi_runtime*)
29 *(.data.efi_runtime*)
Ilias Apalodimas048a9ec2024-03-15 08:43:49 +020030 __efi_runtime_stop = .;
Alexander Graf94a10f22018-06-12 07:48:37 +020031 }
32
33 .text_rest :
34 {
Michal Simekc8cf4712014-02-05 08:06:29 +010035 *(.text*)
36 }
37
38 . = ALIGN(4);
39 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
40
41 . = ALIGN(4);
42 .data : {
43 *(.data*)
44 }
45
46 . = ALIGN(4);
47
48 . = .;
49
50 . = ALIGN(4);
Andrew Scull5a9095c2022-05-30 10:00:04 +000051 __u_boot_list : {
52 KEEP(*(SORT(__u_boot_list*)));
Michal Simekc8cf4712014-02-05 08:06:29 +010053 }
54
Ilias Apalodimas772acf82024-03-15 08:43:51 +020055 .efi_runtime_rel : {
Ilias Apalodimas9b378942024-03-15 08:43:47 +020056 __efi_runtime_rel_start = .;
Alexander Graf94a10f22018-06-12 07:48:37 +020057 *(.rel*.efi_runtime)
58 *(.rel*.efi_runtime.*)
Ilias Apalodimas9b378942024-03-15 08:43:47 +020059 __efi_runtime_rel_stop = .;
Alexander Grafa56b5f12017-07-03 13:41:34 +020060 }
61
Michal Simek02d770a2022-08-31 11:28:59 +020062 . = ALIGN(8);
Ilias Apalodimascdb58392024-03-15 08:43:50 +020063 __image_copy_end = .;
Michal Simekc8cf4712014-02-05 08:06:29 +010064
Ilias Apalodimas45b1bd92024-03-15 08:43:48 +020065 .rel.dyn ALIGN(8) : {
66 __rel_dyn_start = .;
Michal Simekc8cf4712014-02-05 08:06:29 +010067 *(.rel*)
Ilias Apalodimas45b1bd92024-03-15 08:43:48 +020068 __rel_dyn_end = .;
Michal Simekc8cf4712014-02-05 08:06:29 +010069 }
70
Albert ARIBAUD9d25fa42014-02-22 17:53:42 +010071 .end :
72 {
73 *(.__end)
74 }
75
76 _image_binary_end = .;
Michal Simekc8cf4712014-02-05 08:06:29 +010077
78/*
Ilias Apalodimas6d1e1b82024-03-15 08:43:46 +020079 * These sections occupy the same memory, but their lifetimes do
80 * not overlap: U-Boot initializes .bss only after applying dynamic
81 * relocations and therefore after it doesn't need .rel.dyn any more.
Michal Simekc8cf4712014-02-05 08:06:29 +010082 */
Ilias Apalodimas6d1e1b82024-03-15 08:43:46 +020083 .bss ADDR(.rel.dyn) (OVERLAY): {
84 __bss_start = .;
Michal Simekc8cf4712014-02-05 08:06:29 +010085 *(.bss*)
Ilias Apalodimas6d1e1b82024-03-15 08:43:46 +020086 . = ALIGN(8);
87 __bss_end = .;
Michal Simekc8cf4712014-02-05 08:06:29 +010088 }
89
90 /*
Albert ARIBAUD9852cc62014-04-15 16:13:51 +020091 * Zynq needs to discard these sections because the user
Michal Simekc8cf4712014-02-05 08:06:29 +010092 * is expected to pass this image on to tools for boot.bin
93 * generation that require them to be dropped.
94 */
95 /DISCARD/ : { *(.dynsym) }
96 /DISCARD/ : { *(.dynbss*) }
97 /DISCARD/ : { *(.dynstr*) }
98 /DISCARD/ : { *(.dynamic*) }
99 /DISCARD/ : { *(.plt*) }
100 /DISCARD/ : { *(.interp*) }
101 /DISCARD/ : { *(.gnu*) }
102 /DISCARD/ : { *(.ARM.exidx*) }
103 /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
104}