blob: 45d33a68968c6feb9804162d538de2f1d522139e [file] [log] [blame]
John Rigby25a33622011-04-19 10:42:42 +00001/*
2 * Copyright (C) ST-Ericsson SA 2009
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
John Rigby25a33622011-04-19 10:42:42 +00005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/*
11 * High Level Configuration Options
12 * (easy to change)
13 */
14#define CONFIG_U8500
15#define CONFIG_L2_OFF
16
17#define CONFIG_SYS_MEMTEST_START 0x00000000
18#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
John Rigby25a33622011-04-19 10:42:42 +000019
20#define CONFIG_BOARD_EARLY_INIT_F
Helmut Raigerd5a184b2011-10-20 04:19:47 +000021#define CONFIG_BOARD_LATE_INIT
John Rigby25a33622011-04-19 10:42:42 +000022
23/*
24 * Size of malloc() pool
25 */
26#ifdef CONFIG_BOOT_SRAM
27#define CONFIG_ENV_SIZE (32*1024)
28#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024)
29#else
30#define CONFIG_ENV_SIZE (128*1024)
31#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
32#endif
33#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
34
35/*
36 * PL011 Configuration
37 */
38#define CONFIG_PL011_SERIAL
39#define CONFIG_PL011_SERIAL_RLCR
40#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
41
42/*
43 * U8500 UART registers base for 3 serial devices
44 */
45#define CFG_UART0_BASE 0x80120000
46#define CFG_UART1_BASE 0x80121000
47#define CFG_UART2_BASE 0x80007000
48#define CFG_SERIAL0 CFG_UART0_BASE
49#define CFG_SERIAL1 CFG_UART1_BASE
50#define CFG_SERIAL2 CFG_UART2_BASE
51#define CONFIG_PL011_CLOCK 38400000
52#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
53 (void *)CFG_SERIAL2 }
54#define CONFIG_CONS_INDEX 2
55#define CONFIG_BAUDRATE 115200
John Rigby25a33622011-04-19 10:42:42 +000056
57/*
58 * Devices and file systems
59 */
60#define CONFIG_MMC
61#define CONFIG_GENERIC_MMC
62#define CONFIG_DOS_PARTITION
63
64/*
65 * Commands
66 */
67#define CONFIG_CMD_MEMORY
68#define CONFIG_CMD_BOOTD
69#define CONFIG_CMD_BDI
70#define CONFIG_CMD_IMI
71#define CONFIG_CMD_MISC
72#define CONFIG_CMD_RUN
73#define CONFIG_CMD_ECHO
74#define CONFIG_CMD_CONSOLE
75#define CONFIG_CMD_LOADS
76#define CONFIG_CMD_LOADB
77#define CONFIG_CMD_MMC
78#define CONFIG_CMD_FAT
79#define CONFIG_CMD_EXT2
John Rigby25a33622011-04-19 10:42:42 +000080#define CONFIG_CMD_SOURCE
81#define CONFIG_CMD_I2C
82
83#ifndef CONFIG_BOOTDELAY
84#define CONFIG_BOOTDELAY 1
85#endif
86#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
87
88#undef CONFIG_BOOTARGS
89#define CONFIG_BOOTCOMMAND "run emmcboot"
90
91#define CONFIG_EXTRA_ENV_SETTINGS \
92 "verify=n\0" \
93 "loadaddr=0x00100000\0" \
94 "console=ttyAMA2,115200n8\0" \
95 "memargs256=mem=96M@0 mem_modem=32M@96M mem=30M@128M " \
96 "pmem=22M@158M pmem_hwb=44M@180M mem_mali=32@224M\0" \
97 "memargs512=mem=96M@0 mem_modem=32M@96M mem=44M@128M " \
98 "pmem=22M@172M mem=30M@194M mem_mali=32M@224M " \
99 "pmem_hwb=54M@256M mem=202M@310M\0" \
100 "commonargs=setenv bootargs cachepolicy=writealloc noinitrd " \
101 "init=init " \
102 "board_id=${board_id} " \
103 "logo.${logo} " \
104 "startup_graphics=${startup_graphics}\0" \
105 "emmcargs=setenv bootargs ${bootargs} " \
106 "root=/dev/mmcblk0p2 " \
107 "rootdelay=1\0" \
108 "addcons=setenv bootargs ${bootargs} " \
109 "console=${console}\0" \
110 "emmcboot=echo Booting from eMMC ...; " \
111 "run commonargs emmcargs addcons memargs;" \
112 "mmc read 0 ${loadaddr} 0xA0000 0x4000;" \
113 "bootm ${loadaddr}\0" \
114 "flash=mmc init 1;fatload mmc 1 ${loadaddr} flash.scr;" \
115 "source ${loadaddr}\0" \
116 "loaduimage=mmc init 1;fatload mmc 1 ${loadaddr} uImage\0" \
117 "usbtty=cdc_acm\0" \
118 "stdout=serial,usbtty\0" \
119 "stdin=serial,usbtty\0" \
120 "stderr=serial,usbtty\0"
121
122/*
123 * Miscellaneous configurable options
124 */
125
126#define CONFIG_SYS_LONGHELP /* undef to save memory */
127#define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */
128#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
129
130/* Print Buffer Size */
131#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
132 + sizeof(CONFIG_SYS_PROMPT) + 16)
133#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
134#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
135
136#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
137#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
138#define CONFIG_SYS_LOADS_BAUD_CHANGE
139
140#define CONFIG_SYS_HUSH_PARSER
John Rigby25a33622011-04-19 10:42:42 +0000141#define CONFIG_CMDLINE_EDITING
142
143#define CONFIG_SETUP_MEMORY_TAGS 2
144#define CONFIG_INITRD_TAG
145#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
146
147/*
148 * I2C
149 */
150#define CONFIG_U8500_I2C
151#undef CONFIG_HARD_I2C /* I2C with hardware support */
John Rigby25a33622011-04-19 10:42:42 +0000152#define CONFIG_I2C_MULTI_BUS
153#define CONFIG_SYS_I2C_SPEED 100000
154#define CONFIG_SYS_I2C_SLAVE 0 /* slave addr of controller */
155#define CONFIG_SYS_U8500_I2C0_BASE 0x80004000
156#define CONFIG_SYS_U8500_I2C1_BASE 0x80122000
157#define CONFIG_SYS_U8500_I2C2_BASE 0x80128000
158#define CONFIG_SYS_U8500_I2C3_BASE 0x80110000
159#define CONFIG_SYS_U8500_I2C_BUS_MAX 4
160
161#define CONFIG_SYS_I2C_GPIOE_ADDR 0x42 /* GPIO expander chip addr */
162#define CONFIG_TC35892_GPIO
John Rigby25a33622011-04-19 10:42:42 +0000163
164/*
165 * Physical Memory Map
166 */
167#define CONFIG_NR_DRAM_BANKS 1
168#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
169#define PHYS_SDRAM_SIZE_1 0x20000000 /* 512 MB */
170
171/*
172 * additions for new relocation code
173 */
174#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
175#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
176#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
177 CONFIG_SYS_INIT_RAM_SIZE - \
178 GENERATED_GBL_DATA_SIZE)
179#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
180
181/* landing address before relocation */
182#ifndef CONFIG_SYS_TEXT_BASE
183#define CONFIG_SYS_TEXT_BASE 0x0
184#endif
185
186/*
187 * MMC related configs
188 * NB Only externa SD slot is currently supported
189 */
190#define MMC_BLOCK_SIZE 512
191#define CONFIG_ARM_PL180_MMCI
192#define CONFIG_ARM_PL180_MMCI_BASE 0x80126000 /* MMC base for 8500 */
193#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
194#define CONFIG_MMC_DEV_NUM 1
195
196#define CONFIG_CMD_ENV
197#define CONFIG_CMD_SAVEENV /* CMD_ENV is obsolete but used in env_emmc.c */
198#define CONFIG_ENV_IS_IN_MMC
199#define CONFIG_ENV_OFFSET 0x13F80000
200#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
201
202/*
203 * FLASH and environment organization
204 */
205#define CONFIG_SYS_NO_FLASH
206
207/*
208 * base register values for U8500
209 */
210#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock
211 management unit */
212#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
213
214#endif /* __CONFIG_H */