blob: ca5e33379ba91af74ac0c291b502763010ccdf75 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hu0e58b512015-10-26 19:47:50 +08002/*
3 * LayerScape Internal Memory Map
4 *
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +05305 * Copyright 2017-2020 NXP
Mingkai Hu0e58b512015-10-26 19:47:50 +08006 * Copyright 2014 Freescale Semiconductor, Inc.
Mingkai Hu0e58b512015-10-26 19:47:50 +08007 */
8
9#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
10#define __ARCH_FSL_LSCH3_IMMAP_H_
11
Tom Rini376b88a2022-10-28 20:27:13 -040012#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
13#define CFG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
14#define CFG_SYS_FSL_DDR3_ADDR 0x08210000
15#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
16#define CFG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +053017#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
Tom Rini376b88a2022-10-28 20:27:13 -040018#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
Priyanka Jainef76b2e2018-10-29 09:17:09 +000019#else
Tom Rini376b88a2022-10-28 20:27:13 -040020#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
Priyanka Jainef76b2e2018-10-29 09:17:09 +000021#endif
Tom Rini376b88a2022-10-28 20:27:13 -040022#define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
23#define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
24#define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
Kuldeep Singh204a7252019-11-21 17:15:16 +053025#ifndef CONFIG_NXP_LSCH3_2
Yuan Yao52ae4fd2016-12-01 10:13:52 +080026#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
Kuldeep Singh204a7252019-11-21 17:15:16 +053027#else
28#define SYS_NXP_FSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
29#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18
30#define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200
31#endif
Tom Rini376b88a2022-10-28 20:27:13 -040032#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
33#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
Laurentiu Tudore29ca392019-07-30 17:29:56 +030034#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
Priyanka Jain88c25662018-10-29 09:11:29 +000035#ifndef CONFIG_NXP_LSCH3_2
Tom Rini6a5dccc2022-11-16 13:10:41 -050036#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
Priyanka Jain88c25662018-10-29 09:11:29 +000037#endif
Tom Rinidf6a2152022-11-16 13:10:28 -050038#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
39#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
Priyanka Jain3d31ec72016-11-17 12:29:52 +053040#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
Tom Rini376b88a2022-10-28 20:27:13 -040041#define CFG_SYS_FSL_TIMER_ADDR 0x023e0000
42#define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \
Mingkai Hu0e58b512015-10-26 19:47:50 +080043 0x18A0)
Tom Rini376b88a2022-10-28 20:27:13 -040044#define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0)
45#define FSL_LSCH3_SVR (CFG_SYS_FSL_GUTS_ADDR + 0xA4)
Mingkai Hu0e58b512015-10-26 19:47:50 +080046
Tom Rini376b88a2022-10-28 20:27:13 -040047#define CFG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
48#define CFG_SYS_FSL_WRIOP1_MDIO1 (CFG_SYS_FSL_WRIOP1_ADDR + 0x16000)
49#define CFG_SYS_FSL_WRIOP1_MDIO2 (CFG_SYS_FSL_WRIOP1_ADDR + 0x17000)
50#define CFG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
Mingkai Hu0e58b512015-10-26 19:47:50 +080051
Tom Rini376b88a2022-10-28 20:27:13 -040052#define CFG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
53#define CFG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
54#define CFG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
Mingkai Hu0e58b512015-10-26 19:47:50 +080055
56#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
57#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
58#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
59#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
Priyanka Jain88c25662018-10-29 09:11:29 +000060#ifdef CONFIG_NXP_LSCH3_2
61#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000)
62#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000)
63#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000)
64#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000)
65#endif
Priyanka Jaind1587182017-04-25 10:12:31 +053066#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
67#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
68#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
Mingkai Hu0e58b512015-10-26 19:47:50 +080069
Tom Rini6a5dccc2022-11-16 13:10:41 -050070#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
71#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
Mingkai Hu0e58b512015-10-26 19:47:50 +080072
73/* TZ Address Space Controller Definitions */
74#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
75#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
76#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
77#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
78#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
79#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
80#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
81#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
82#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
83#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
84#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
85#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
86#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
87
Laurentiu Tudore29ca392019-07-30 17:29:56 +030088/* EDMA */
89#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c0000)
90
Tang Yuantian57894be2015-12-09 15:32:18 +080091/* SATA */
92#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
93#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
Laurentiu Tudor15858352019-10-18 09:01:54 +000094#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000)
95#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000)
Tang Yuantian57894be2015-12-09 15:32:18 +080096
Laurentiu Tudore29ca392019-07-30 17:29:56 +030097/* QDMA */
98#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
99#define QMAN_CQSIDR_REG 0x20a80
100
101/* DISPLAY */
102#define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e080000)
103
104/* GPU */
105#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000)
106
Saksham Jain62888be2016-03-23 16:24:32 +0530107/* SFP */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500108#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
Saksham Jain62888be2016-03-23 16:24:32 +0530109
Saksham Jain6ae7f582016-03-23 16:24:33 +0530110/* SEC */
Tom Rini376b88a2022-10-28 20:27:13 -0400111#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull
112#define CFG_SYS_FSL_JR0_OFFSET 0x07010000ull
113#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
Laurentiu Tudor32f4c162019-07-30 17:29:55 +0300114#define FSL_SEC_JR1_OFFSET 0x07020000ull
115#define FSL_SEC_JR2_OFFSET 0x07030000ull
116#define FSL_SEC_JR3_OFFSET 0x07040000ull
Tom Rini376b88a2022-10-28 20:27:13 -0400117#define CFG_SYS_FSL_SEC_ADDR \
118 (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
119#define CFG_SYS_FSL_JR0_ADDR \
120 (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
Laurentiu Tudor32f4c162019-07-30 17:29:55 +0300121#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
122#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
123#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
124#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
Saksham Jain6ae7f582016-03-23 16:24:33 +0530125
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000126#ifdef CONFIG_TFABOOT
Priyanka Jain88c25662018-10-29 09:11:29 +0000127#ifdef CONFIG_NXP_LSCH3_2
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000128/* RCW_SRC field in Power-On Reset Control Register 1 */
129#define RCW_SRC_MASK 0x07800000
130#define RCW_SRC_BIT 23
131
132/* CFG_RCW_SRC[3:0] */
133#define RCW_SRC_TYPE_MASK 0x8
134#define RCW_SRC_ADDR_OFFSET_8MB 0x800000
135
136/* RCW SRC HARDCODED */
137#define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */
138
139#define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */
140#define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */
141#define RCW_SRC_I2C1_VAL 0xa /* 0xa */
142#define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */
143#define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */
144#define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */
145#define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */
146#define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */
147#else
148#define RCW_SRC_MASK (0xFF800000)
149#define RCW_SRC_BIT 23
150/* CFG_RCW_SRC[6:0] */
151#define RCW_SRC_TYPE_MASK (0x70)
152
153/* RCW SRC HARDCODED */
154#define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */
155/* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */
156
157/* RCW SRC NOR */
158#define RCW_SRC_NOR_VAL (0x20)
159#define NOR_TYPE_MASK (0x10)
160#define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */
161#define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */
162
163/* RCW SRC Serial Flash
164 * 1. SERIAL NOR (QSPI)
165 * 2. OTHERS (SD/MMC, SPI, I2C1
166 */
167#define RCW_SRC_SERIAL_MASK (0x7F)
168#define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */
169#define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */
170#define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */
171#define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */
172#endif
173#endif
174
Saksham Jain6ae7f582016-03-23 16:24:33 +0530175/* Security Monitor */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500176#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
Saksham Jain6ae7f582016-03-23 16:24:33 +0530177
Saksham Jain5d8ffe12016-03-23 16:24:40 +0530178/* MMU 500 */
179#define SMMU_SCR0 (SMMU_BASE + 0x0)
180#define SMMU_SCR1 (SMMU_BASE + 0x4)
181#define SMMU_SCR2 (SMMU_BASE + 0x8)
182#define SMMU_SACR (SMMU_BASE + 0x10)
183#define SMMU_IDR0 (SMMU_BASE + 0x20)
184#define SMMU_IDR1 (SMMU_BASE + 0x24)
185
186#define SMMU_NSCR0 (SMMU_BASE + 0x400)
187#define SMMU_NSCR2 (SMMU_BASE + 0x408)
188#define SMMU_NSACR (SMMU_BASE + 0x410)
189
190#define SCR0_CLIENTPD_MASK 0x00000001
191#define SCR0_USFCFG_MASK 0x00000400
192
Saksham Jain6ae7f582016-03-23 16:24:33 +0530193
Mingkai Hu0e58b512015-10-26 19:47:50 +0800194/* PCIe */
Tom Rini56af6592022-11-16 13:10:33 -0500195#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
196#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530197#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
Hou Zhiqiangd08f9702019-04-08 10:15:41 +0000198#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
199#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
200#endif
201
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530202#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
Tom Rini56af6592022-11-16 13:10:33 -0500203#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
204#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
205#define CFG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
206#define CFG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL
Hou Zhiqiangd08f9702019-04-08 10:15:41 +0000207#define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL
208#define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL
209#elif CONFIG_ARCH_LS1088A
Tom Rini56af6592022-11-16 13:10:33 -0500210#define CFG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
211#define CFG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
212#define CFG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
Yuantian Tang4aefa162019-04-10 16:43:33 +0800213#elif CONFIG_ARCH_LS1028A
Tom Rini56af6592022-11-16 13:10:33 -0500214#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
215#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
216#define CFG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL
Alex Marginean0d5ed8f2019-06-07 17:03:07 +0300217/* this is used by integrated PCI on LS1028, includes ECAM and register space */
Tom Rini56af6592022-11-16 13:10:33 -0500218#define CFG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL
Hou Zhiqiang19143122017-09-04 10:47:52 +0800219#else
Tom Rini56af6592022-11-16 13:10:33 -0500220#define CFG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
221#define CFG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
222#define CFG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
223#define CFG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
Hou Zhiqiang19143122017-09-04 10:47:52 +0800224#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +0800225
226/* Device Configuration */
227#define DCFG_BASE 0x01e00000
228#define DCFG_PORSR1 0x000
229#define DCFG_PORSR1_RCW_SRC 0xff800000
Michael Walle98fbb562022-05-30 23:02:05 +0200230#define DCFG_PORSR1_RCW_SRC_SDHC1 0x04000000
231#define DCFG_PORSR1_RCW_SRC_SDHC2 0x04800000
232#define DCFG_PORSR1_RCW_SRC_I2C 0x05000000
233#define DCFG_PORSR1_RCW_SRC_FSPI_NOR 0x07800000
Mingkai Hu0e58b512015-10-26 19:47:50 +0800234#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
Yinbo Zhu96cd3d42020-04-14 17:24:48 +0800235#define DCFG_RCWSR12 0x12c
236#define DCFG_RCWSR12_SDHC_SHIFT 24
237#define DCFG_RCWSR12_SDHC_MASK 0x7
Mingkai Hu0e58b512015-10-26 19:47:50 +0800238#define DCFG_RCWSR13 0x130
Yinbo Zhu96cd3d42020-04-14 17:24:48 +0800239#define DCFG_RCWSR13_SDHC_SHIFT 3
240#define DCFG_RCWSR13_SDHC_MASK 0x7
Mingkai Hu0e58b512015-10-26 19:47:50 +0800241#define DCFG_RCWSR13_DSPI (0 << 8)
Yuan Yao86f42d72016-06-08 18:24:57 +0800242#define DCFG_RCWSR15 0x138
243#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
Mingkai Hu0e58b512015-10-26 19:47:50 +0800244
245#define DCFG_DCSR_BASE 0X700100000ULL
246#define DCFG_DCSR_PORCR1 0x000
247
Shaohui Xie8c7ce822016-01-28 15:38:15 +0800248/* Interrupt Sampling Control */
249#define ISC_BASE 0x01F70000
250#define IRQCR_OFFSET 0x14
251
Mingkai Hu0e58b512015-10-26 19:47:50 +0800252/* Supplemental Configuration */
253#define SCFG_BASE 0x01fc0000
254#define SCFG_USB3PRM1CR 0x000
Sriram Dash01820952016-06-13 09:58:36 +0530255#define SCFG_USB3PRM1CR_INIT 0x27672b2a
Ran Wangb358b7b2017-09-04 18:46:48 +0800256#define SCFG_USB_TXVREFTUNE 0x9
Ran Wang9e8fabc2017-09-04 18:46:49 +0800257#define SCFG_USB_SQRXTUNE_MASK 0x7
Yuan Yao2ec85842016-06-08 18:24:52 +0800258#define SCFG_QSPICLKCTLR 0x10
Mingkai Hu0e58b512015-10-26 19:47:50 +0800259
Ran Wang3ba69482017-09-04 18:46:51 +0800260#define DCSR_BASE 0x700000000ULL
261#define DCSR_USB_PHY1 0x4600000
262#define DCSR_USB_PHY2 0x4610000
263#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
264#define USB_PHY_RX_EQ_VAL_1 0x0000
265#define USB_PHY_RX_EQ_VAL_2 0x0080
Ran Wangd0270dc2019-11-26 11:40:40 +0800266#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
267 defined(CONFIG_ARCH_LS1028A)
Ran Wang3ba69482017-09-04 18:46:51 +0800268#define USB_PHY_RX_EQ_VAL_3 0x0380
269#define USB_PHY_RX_EQ_VAL_4 0x0b80
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530270#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
Ran Wangd0270dc2019-11-26 11:40:40 +0800271#define USB_PHY_RX_EQ_VAL_3 0x0080
272#define USB_PHY_RX_EQ_VAL_4 0x0880
273#endif
Ran Wange118acb2019-05-14 17:34:56 +0800274#define DCSR_USB_IOCR1 0x108004
275#define DCSR_USB_PCSTXSWINGFULL 0x71
Ran Wang3ba69482017-09-04 18:46:51 +0800276
Mingkai Hu0e58b512015-10-26 19:47:50 +0800277#define TP_ITYP_AV 0x00000001 /* Initiator available */
278#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
279#define TP_ITYP_TYPE_ARM 0x0
280#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
281#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
282#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
283#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
284#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
285#define TY_ITYP_VER_A7 0x1
286#define TY_ITYP_VER_A53 0x2
287#define TY_ITYP_VER_A57 0x3
Alison Wang79808392016-07-05 16:01:52 +0800288#define TY_ITYP_VER_A72 0x4
Mingkai Hu0e58b512015-10-26 19:47:50 +0800289
290#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
291#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
292#define TP_INIT_PER_CLUSTER 4
293/* This is chassis generation 3 */
Priyanka Jain96b001f2016-11-17 12:29:51 +0530294#ifndef __ASSEMBLY__
Mingkai Hu0e58b512015-10-26 19:47:50 +0800295struct sys_info {
296 unsigned long freq_processor[CONFIG_MAX_CPUS];
Hou Zhiqiang3a76dd52017-01-10 16:44:16 +0800297 /* frequency of platform PLL */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800298 unsigned long freq_systembus;
299 unsigned long freq_ddrbus;
Yinbo Zhu3761ffc2019-07-16 15:09:06 +0800300 unsigned long freq_cga_m2;
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530301#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
Mingkai Hu0e58b512015-10-26 19:47:50 +0800302 unsigned long freq_ddrbus2;
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530303#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +0800304 unsigned long freq_localbus;
305 unsigned long freq_qe;
306#ifdef CONFIG_SYS_DPAA_FMAN
Tom Rini0a2bac72022-11-16 13:10:29 -0500307 unsigned long freq_fman[CFG_SYS_NUM_FMAN];
Mingkai Hu0e58b512015-10-26 19:47:50 +0800308#endif
309#ifdef CONFIG_SYS_DPAA_QBMAN
310 unsigned long freq_qman;
311#endif
312#ifdef CONFIG_SYS_DPAA_PME
313 unsigned long freq_pme;
314#endif
315};
316
317/* Global Utilities Block */
318struct ccsr_gur {
319 u32 porsr1; /* POR status 1 */
320 u32 porsr2; /* POR status 2 */
321 u8 res_008[0x20-0x8];
322 u32 gpporcr1; /* General-purpose POR configuration */
323 u32 gpporcr2; /* General-purpose POR configuration 2 */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530324 u32 gpporcr3;
325 u32 gpporcr4;
326 u8 res_030[0x60-0x30];
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530327#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530328#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
Rajesh Bhagat170eecf2018-01-17 16:13:05 +0530329#if defined(CONFIG_ARCH_LS1088A)
330#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
331#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
332#else
333#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
334#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
335#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +0800336 u32 dcfg_fusesr; /* Fuse status register */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530337 u8 res_064[0x70-0x64];
338 u32 devdisr; /* Device disable control 1 */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800339 u32 devdisr2; /* Device disable control 2 */
340 u32 devdisr3; /* Device disable control 3 */
341 u32 devdisr4; /* Device disable control 4 */
342 u32 devdisr5; /* Device disable control 5 */
343 u32 devdisr6; /* Device disable control 6 */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530344 u8 res_088[0x94-0x88];
345 u32 coredisr; /* Device disable control 7 */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800346#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
347#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
348#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
349#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
350#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
351#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
352#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
353#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
354#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
355#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
356#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
357#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
358#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
359#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
360#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
361#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
362#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
363#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
364#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
365#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
366#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
367#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
368#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
369#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
Mingkai Hu0e58b512015-10-26 19:47:50 +0800370 u8 res_098[0xa0-0x98];
371 u32 pvr; /* Processor version */
372 u32 svr; /* System version */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530373 u8 res_0a8[0x100-0xa8];
374 u32 rcwsr[30]; /* Reset control word status */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800375
376#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
377#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
378#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
379#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
380#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
381#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
Prabhakar Kushwaha57f7f2ed2017-02-15 20:40:35 +0530382
383#if defined(CONFIG_ARCH_LS2080A)
Mingkai Hu0e58b512015-10-26 19:47:50 +0800384#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
385#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
386#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
387#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
Prabhakar Kushwaha57f7f2ed2017-02-15 20:40:35 +0530388#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
389#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
390#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
391#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000392#define FSL_CHASSIS3_SRDS1_REGSR 29
393#define FSL_CHASSIS3_SRDS2_REGSR 29
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530394#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000395#define FSL_CHASSIS3_EC1_REGSR 27
396#define FSL_CHASSIS3_EC2_REGSR 27
397#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003
398#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0
Razvan Ionut Cirjan912f2d82020-10-23 16:20:38 +0530399#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x0000000C
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000400#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2
401#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000
402#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
403#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000
404#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21
405#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000
406#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26
407#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
408#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
409#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
410#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
411#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK
412#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT
Prabhakar Kushwaha57f7f2ed2017-02-15 20:40:35 +0530413#define FSL_CHASSIS3_SRDS1_REGSR 29
414#define FSL_CHASSIS3_SRDS2_REGSR 29
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000415#define FSL_CHASSIS3_SRDS3_REGSR 29
Pankaj Bansal338baa32019-02-08 10:29:58 +0000416#define FSL_CHASSIS3_RCWSR12_REGSR 12
417#define FSL_CHASSIS3_RCWSR13_REGSR 13
418#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000
419#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
420#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038
421#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
422#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00
423#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9
Ashish Kumarb25faa22017-08-31 16:12:53 +0530424#elif defined(CONFIG_ARCH_LS1088A)
Ashish Kumarec455e22017-08-31 16:37:31 +0530425#define FSL_CHASSIS3_EC1_REGSR 26
426#define FSL_CHASSIS3_EC2_REGSR 26
427#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007
428#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0
429#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038
430#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3
Ashish Kumarb25faa22017-08-31 16:12:53 +0530431#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
432#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
433#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
434#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0
435#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
436#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
437#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
438#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
439#define FSL_CHASSIS3_SRDS1_REGSR 29
440#define FSL_CHASSIS3_SRDS2_REGSR 30
Yuantian Tang4aefa162019-04-10 16:43:33 +0800441#elif defined(CONFIG_ARCH_LS1028A)
442#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
443#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
444#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
445#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
446#define FSL_CHASSIS3_SRDS1_REGSR 29
Prabhakar Kushwaha57f7f2ed2017-02-15 20:40:35 +0530447#endif
Saksham Jain6ae7f582016-03-23 16:24:33 +0530448#define RCW_SB_EN_REG_INDEX 9
449#define RCW_SB_EN_MASK 0x00000400
Mingkai Hu0e58b512015-10-26 19:47:50 +0800450
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530451 u8 res_178[0x200-0x178];
452 u32 scratchrw[16]; /* Scratch Read/Write */
453 u8 res_240[0x300-0x240];
Mingkai Hu0e58b512015-10-26 19:47:50 +0800454 u32 scratchw1r[4]; /* Scratch Read (Write once) */
455 u8 res_310[0x400-0x310];
456 u32 bootlocptrl; /* Boot location pointer low-order addr */
457 u32 bootlocptrh; /* Boot location pointer high-order addr */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530458 u8 res_408[0x520-0x408];
459 u32 usb1_amqr;
460 u32 usb2_amqr;
461 u8 res_528[0x530-0x528]; /* add more registers when needed */
462 u32 sdmm1_amqr;
Laurentiu Tudor01dc5472019-07-30 17:29:59 +0300463 u32 sdmm2_amqr;
464 u8 res_538[0x550 - 0x538]; /* add more registers when needed */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530465 u32 sata1_amqr;
466 u32 sata2_amqr;
Laurentiu Tudor7085d072019-10-18 09:01:55 +0000467 u32 sata3_amqr;
468 u32 sata4_amqr;
469 u8 res_560[0x570 - 0x560]; /* add more registers when needed */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530470 u32 misc1_amqr;
471 u8 res_574[0x590-0x574]; /* add more registers when needed */
472 u32 spare1_amqr;
473 u32 spare2_amqr;
Laurentiu Tudor01dc5472019-07-30 17:29:59 +0300474 u32 spare3_amqr;
475 u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530476 u32 gencr[7]; /* General Control Registers */
477 u8 res_63c[0x640-0x63c]; /* add more registers when needed */
478 u32 cgensr1; /* Core General Status Register */
479 u8 res_644[0x660-0x644]; /* add more registers when needed */
480 u32 cgencr1; /* Core General Control Register */
481 u8 res_664[0x740-0x664]; /* add more registers when needed */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800482 u32 tp_ityp[64]; /* Topology Initiator Type Register */
483 struct {
484 u32 upper;
485 u32 lower;
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530486 } tp_cluster[4]; /* Core cluster n Topology Register */
487 u8 res_864[0x920-0x864]; /* add more registers when needed */
488 u32 ioqoscr[8]; /*I/O Quality of Services Register */
489 u32 uccr;
490 u8 res_944[0x960-0x944]; /* add more registers when needed */
491 u32 ftmcr;
492 u8 res_964[0x990-0x964]; /* add more registers when needed */
493 u32 coredisablesr;
494 u8 res_994[0xa00-0x994]; /* add more registers when needed */
495 u32 sdbgcr; /*Secure Debug Confifuration Register */
496 u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
497 u32 ipbrr1;
498 u32 ipbrr2;
499 u8 res_858[0x1000-0xc00];
Mingkai Hu0e58b512015-10-26 19:47:50 +0800500};
501
Mingkai Hu0e58b512015-10-26 19:47:50 +0800502struct ccsr_clk_cluster_group {
503 struct {
504 u8 res_00[0x10];
505 u32 csr;
506 u8 res_14[0x20-0x14];
507 } hwncsr[3];
508 u8 res_60[0x80-0x60];
509 struct {
510 u32 gsr;
511 u8 res_84[0xa0-0x84];
512 } pllngsr[3];
513 u8 res_e0[0x100-0xe0];
514};
515
516struct ccsr_clk_ctrl {
517 struct {
518 u32 csr; /* core cluster n clock control status */
519 u8 res_04[0x20-0x04];
520 } clkcncsr[8];
521};
522
523struct ccsr_reset {
524 u32 rstcr; /* 0x000 */
525 u32 rstcrsp; /* 0x004 */
526 u8 res_008[0x10-0x08]; /* 0x008 */
527 u32 rstrqmr1; /* 0x010 */
528 u32 rstrqmr2; /* 0x014 */
529 u32 rstrqsr1; /* 0x018 */
530 u32 rstrqsr2; /* 0x01c */
531 u32 rstrqwdtmrl; /* 0x020 */
532 u32 rstrqwdtmru; /* 0x024 */
533 u8 res_028[0x30-0x28]; /* 0x028 */
534 u32 rstrqwdtsrl; /* 0x030 */
535 u32 rstrqwdtsru; /* 0x034 */
536 u8 res_038[0x60-0x38]; /* 0x038 */
537 u32 brrl; /* 0x060 */
538 u32 brru; /* 0x064 */
539 u8 res_068[0x80-0x68]; /* 0x068 */
540 u32 pirset; /* 0x080 */
541 u32 pirclr; /* 0x084 */
542 u8 res_088[0x90-0x88]; /* 0x088 */
543 u32 brcorenbr; /* 0x090 */
544 u8 res_094[0x100-0x94]; /* 0x094 */
545 u32 rcw_reqr; /* 0x100 */
546 u32 rcw_completion; /* 0x104 */
547 u8 res_108[0x110-0x108]; /* 0x108 */
548 u32 pbi_reqr; /* 0x110 */
549 u32 pbi_completion; /* 0x114 */
550 u8 res_118[0xa00-0x118]; /* 0x118 */
551 u32 qmbm_warmrst; /* 0xa00 */
552 u32 soc_warmrst; /* 0xa04 */
553 u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
554 u32 ip_rev1; /* 0xbf8 */
555 u32 ip_rev2; /* 0xbfc */
556};
Sriram Dash9282d262016-06-13 09:58:32 +0530557
Rajesh Bhagat814e0772018-01-17 16:13:00 +0530558struct ccsr_serdes {
559 struct {
560 u32 rstctl; /* Reset Control Register */
561 u32 pllcr0; /* PLL Control Register 0 */
562 u32 pllcr1; /* PLL Control Register 1 */
563 u32 pllcr2; /* PLL Control Register 2 */
564 u32 pllcr3; /* PLL Control Register 3 */
565 u32 pllcr4; /* PLL Control Register 4 */
566 u32 pllcr5; /* PLL Control Register 5 */
567 u8 res[0x20 - 0x1c];
568 } bank[2];
569 u8 res1[0x90 - 0x40];
570 u32 srdstcalcr; /* TX Calibration Control */
571 u32 srdstcalcr1; /* TX Calibration Control1 */
572 u8 res2[0xa0 - 0x98];
573 u32 srdsrcalcr; /* RX Calibration Control */
574 u32 srdsrcalcr1; /* RX Calibration Control1 */
575 u8 res3[0xb0 - 0xa8];
576 u32 srdsgr0; /* General Register 0 */
577 u8 res4[0x800 - 0xb4];
578 struct serdes_lane {
579 u32 gcr0; /* General Control Register 0 */
580 u32 gcr1; /* General Control Register 1 */
581 u32 gcr2; /* General Control Register 2 */
582 u32 ssc0; /* Speed Switch Control 0 */
583 u32 rec0; /* Receive Equalization Control 0 */
584 u32 rec1; /* Receive Equalization Control 1 */
585 u32 tec0; /* Transmit Equalization Control 0 */
586 u32 ssc1; /* Speed Switch Control 1 */
587 u8 res1[0x840 - 0x820];
588 } lane[8];
589 u8 res5[0x19fc - 0xa00];
590};
591
Biwen Lidb5d53b2021-02-05 19:01:47 +0800592struct ccsr_gpio {
593 u32 gpdir;
594 u32 gpodr;
595 u32 gpdat;
596 u32 gpier;
597 u32 gpimr;
598 u32 gpicr;
599 u32 gpibe;
600};
601
Simon Glass559f1a82020-05-10 11:40:12 -0600602#endif /*__ASSEMBLY__ */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800603#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */