armv8: lx2162a: Add Soc changes to support LX2162A
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.
LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
[Fixed whitespace errors]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 24a64b7..b61666e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -2,7 +2,7 @@
/*
* LayerScape Internal Memory Map
*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014 Freescale Semiconductor, Inc.
*/
@@ -15,7 +15,7 @@
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
#else
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
@@ -198,12 +198,12 @@
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
#endif
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
@@ -267,7 +267,7 @@
defined(CONFIG_ARCH_LS1028A)
#define USB_PHY_RX_EQ_VAL_3 0x0380
#define USB_PHY_RX_EQ_VAL_4 0x0b80
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define USB_PHY_RX_EQ_VAL_3 0x0080
#define USB_PHY_RX_EQ_VAL_4 0x0880
#endif
@@ -391,7 +391,7 @@
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define FSL_CHASSIS3_EC1_REGSR 27
#define FSL_CHASSIS3_EC2_REGSR 27
#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003