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git01.mediatek.com / filogic / uboot / 4f98fba27f0264e06b3c7eada42a6d5e6f5bf71a / . / configs / puma-rk3399_defconfig
blob: f62cfc9aab7c00e294f81aac77426ef293d2cec8 [file] [log] [blame]
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]5CONFIG_SYS_TEXT_BASE=0x00200000
Simon Glass035939e2021-07-10 21:14:30 -0600[diff] [blame]6CONFIG_SPL_GPIO=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=1
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]8CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]10CONFIG_SPL_TEXT_BASE=0xff8c2000
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]11CONFIG_ROCKCHIP_RK3399=y
Philipp Tomsich7427c392017-11-24 14:44:59 +0100[diff] [blame]12CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
Tom Rini79f4eea2017-05-01 11:41:11 -0400[diff] [blame]13CONFIG_TARGET_PUMA_RK3399=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]14CONFIG_DEBUG_UART_BASE=0xFF180000
15CONFIG_DEBUG_UART_CLOCK=24000000
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]16CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]17CONFIG_SPL_SPI=y
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]18CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]19CONFIG_DEBUG_UART=y
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]20CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
21CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]22CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]23CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]24CONFIG_MISC_INIT_R=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]25CONFIG_SPL_MAX_SIZE=0x2e000
26CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame]27CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
28CONFIG_SPL_BSS_START_ADDR=0xff8e0000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]29CONFIG_SPL_BSS_MAX_SIZE=0x10000
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]30# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]31# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
32CONFIG_SPL_STACK=0xff8effff
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]33CONFIG_SPL_STACK_R=y
34CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
35CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]36CONFIG_SPL_I2C=y
Simon Glasse91ac4c2021-07-10 21:14:24 -0600[diff] [blame]37CONFIG_SPL_POWER=y
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]38CONFIG_SPL_SPI_LOAD=y
Tom Rinie22fa4f2021-08-10 15:08:46 -0400[diff] [blame]39CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]40CONFIG_CMD_BOOTZ=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]41CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]42CONFIG_CMD_I2C=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]43CONFIG_CMD_MMC=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]44CONFIG_CMD_SPI=y
45CONFIG_CMD_USB=y
46# CONFIG_CMD_SETEXPR is not set
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]47CONFIG_CMD_BMP=y
48CONFIG_CMD_CACHE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]49CONFIG_CMD_TIME=y
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]50CONFIG_CMD_PMIC=y
51CONFIG_CMD_REGULATOR=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]52CONFIG_SPL_OF_CONTROL=y
Philipp Tomsich00fd83f2017-09-12 17:32:29 +0200[diff] [blame]53CONFIG_OF_LIVE=y
Quentin Schulz286e96c2022-09-15 11:14:23 +0200[diff] [blame]54CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]55CONFIG_ENV_OVERWRITE=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]56CONFIG_ENV_IS_IN_MMC=y
Quentin Schulz4f98fba2022-09-15 11:14:26 +0200[diff] [blame^]57CONFIG_ENV_IS_IN_SPI_FLASH=y
58CONFIG_ENV_SPI_MAX_HZ=50000000
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]59CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinieb1f9092020-07-24 17:14:47 -0400[diff] [blame]60CONFIG_SYS_MMC_ENV_DEV=1
Tom Riniae21e7f2021-08-30 09:16:29 -0400[diff] [blame]61CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
Hugh Cole-Baker2d338232020-11-22 13:03:46 +0000[diff] [blame]62CONFIG_SPL_DM_SEQ_ALIAS=y
Quentin Schulza0fb0bd2022-09-15 11:14:22 +0200[diff] [blame]63CONFIG_GPIO_HOG=y
64CONFIG_SPL_GPIO_HOG=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]65CONFIG_ROCKCHIP_GPIO=y
Philipp Tomsicha4dbfc32017-05-31 18:18:49 +0200[diff] [blame]66CONFIG_SYS_I2C_ROCKCHIP=y
Philipp Tomsichf781e802017-05-05 19:21:41 +0200[diff] [blame]67CONFIG_MISC=y
68CONFIG_ROCKCHIP_EFUSE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]69CONFIG_MMC_DW=y
70CONFIG_MMC_DW_ROCKCHIP=y
71CONFIG_MMC_SDHCI=y
Philipp Tomsichdf23b0d2018-03-26 19:59:08 +0200[diff] [blame]72CONFIG_MMC_SDHCI_SDMA=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]73CONFIG_MMC_SDHCI_ROCKCHIP=y
Hugh Cole-Baker2d338232020-11-22 13:03:46 +0000[diff] [blame]74CONFIG_SF_DEFAULT_BUS=1
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]75CONFIG_SF_DEFAULT_SPEED=20000000
Philipp Tomsichb1c07ff2019-02-03 15:59:23 +0100[diff] [blame]76CONFIG_SPI_FLASH_GIGADEVICE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]77CONFIG_SPI_FLASH_WINBOND=y
78CONFIG_PHY_MICREL=y
Philipp Tomsich87321152017-10-30 14:44:55 +0100[diff] [blame]79CONFIG_PHY_MICREL_KSZ90X1=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]80CONFIG_ETH_DESIGNWARE=y
81CONFIG_GMAC_ROCKCHIP=y
Heiko Stuebnerf9fb9552020-06-05 12:06:43 +0200[diff] [blame]82CONFIG_PHY_ROCKCHIP_INNO_USB2=y
83CONFIG_PHY_ROCKCHIP_TYPEC=y
Philipp Tomsich3baf4402018-11-30 20:00:09 +0100[diff] [blame]84CONFIG_DM_PMIC_FAN53555=y
Philipp Tomsich222464f2017-05-31 18:18:46 +0200[diff] [blame]85CONFIG_PMIC_RK8XX=y
Simon Glass6343ffb2021-08-08 12:20:25 -0600[diff] [blame]86CONFIG_SPL_PMIC_RK8XX=y
Christoph Muellner8356c892019-01-02 15:09:17 +0100[diff] [blame]87CONFIG_REGULATOR_PWM=y
Philipp Tomsich222464f2017-05-31 18:18:46 +0200[diff] [blame]88CONFIG_REGULATOR_RK8XX=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]89CONFIG_PWM_ROCKCHIP=y
Heiko Stuebnerf9fb9552020-06-05 12:06:43 +0200[diff] [blame]90CONFIG_DM_RESET=y
Klaus Gogercda97be2018-04-13 10:54:28 +0200[diff] [blame]91CONFIG_DM_RTC=y
92CONFIG_RTC_ISL1208=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]93CONFIG_DEBUG_UART_SHIFT=2
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]94CONFIG_ROCKCHIP_SPI=y
95CONFIG_SYSRESET=y
96CONFIG_USB=y
97CONFIG_USB_XHCI_HCD=y
98CONFIG_USB_XHCI_DWC3=y
99CONFIG_USB_EHCI_HCD=y
100CONFIG_USB_EHCI_GENERIC=y
Heiko Stuebnerf9fb9552020-06-05 12:06:43 +0200[diff] [blame]101CONFIG_USB_DWC3=y
102CONFIG_USB_DWC3_GENERIC=y
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]103CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]104CONFIG_USB_ETHER_ASIX=y
105CONFIG_USB_ETHER_ASIX88179=y
106CONFIG_USB_ETHER_MCS7830=y
107CONFIG_USB_ETHER_RTL8152=y
108CONFIG_USB_ETHER_SMSC95XX=y
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]109CONFIG_DM_VIDEO=y
Anatolij Gustschindba36702020-02-04 22:43:06 +0100[diff] [blame]110# CONFIG_VIDEO_BPP8 is not set
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]111CONFIG_DISPLAY=y
112CONFIG_VIDEO_ROCKCHIP=y
113CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Patrick Delaunayb1f17632020-09-28 11:30:16 +0200[diff] [blame]114CONFIG_BMP_16BPP=y
115CONFIG_BMP_24BPP=y
116CONFIG_BMP_32BPP=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]117CONFIG_ERRNO_STR=y