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git01.mediatek.com / filogic / uboot / e91ac4c2cdbec57b096e72a0c5dc96f727a5d8e5 / . / configs / puma-rk3399_defconfig
blob: d222447e44be7821141d2ce01f842d969b8800d4 [file] [log] [blame]
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x00200000
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]4CONFIG_SPL_GPIO_SUPPORT=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]5CONFIG_NR_DRAM_BANKS=1
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]6CONFIG_ENV_OFFSET=0x3F8000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]7CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]9CONFIG_SPL_TEXT_BASE=0xff8c2000
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]10CONFIG_ROCKCHIP_RK3399=y
Philipp Tomsich7427c392017-11-24 14:44:59 +0100[diff] [blame]11CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
Tom Rini79f4eea2017-05-01 11:41:11 -0400[diff] [blame]12CONFIG_TARGET_PUMA_RK3399=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]13CONFIG_DEBUG_UART_BASE=0xFF180000
14CONFIG_DEBUG_UART_CLOCK=24000000
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]15CONFIG_SPL_SPI_FLASH_SUPPORT=y
16CONFIG_SPL_SPI_SUPPORT=y
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]17CONFIG_DEBUG_UART=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]18CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]19CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]20CONFIG_MISC_INIT_R=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]21# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]22CONFIG_SPL_STACK_R=y
23CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
24CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]25CONFIG_SPL_I2C_SUPPORT=y
Simon Glasse91ac4c2021-07-10 21:14:24 -0600[diff] [blame^]26CONFIG_SPL_POWER=y
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]27CONFIG_SPL_SPI_LOAD=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]28CONFIG_CMD_BOOTZ=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]29CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]30CONFIG_CMD_I2C=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]31CONFIG_CMD_MMC=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]32CONFIG_CMD_SPI=y
33CONFIG_CMD_USB=y
34# CONFIG_CMD_SETEXPR is not set
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]35CONFIG_CMD_BMP=y
36CONFIG_CMD_CACHE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]37CONFIG_CMD_TIME=y
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]38CONFIG_CMD_PMIC=y
39CONFIG_CMD_REGULATOR=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]40CONFIG_SPL_OF_CONTROL=y
Philipp Tomsich00fd83f2017-09-12 17:32:29 +0200[diff] [blame]41CONFIG_OF_LIVE=y
Philipp Tomsich57806cb2017-05-31 18:18:50 +0200[diff] [blame]42CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]43CONFIG_ENV_OVERWRITE=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]44CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]45CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinieb1f9092020-07-24 17:14:47 -0400[diff] [blame]46CONFIG_SYS_MMC_ENV_DEV=1
Hugh Cole-Baker2d338232020-11-22 13:03:46 +0000[diff] [blame]47CONFIG_SPL_DM_SEQ_ALIAS=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]48CONFIG_ROCKCHIP_GPIO=y
Philipp Tomsicha4dbfc32017-05-31 18:18:49 +0200[diff] [blame]49CONFIG_SYS_I2C_ROCKCHIP=y
Philipp Tomsichf781e802017-05-05 19:21:41 +0200[diff] [blame]50CONFIG_MISC=y
51CONFIG_ROCKCHIP_EFUSE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]52CONFIG_MMC_DW=y
53CONFIG_MMC_DW_ROCKCHIP=y
54CONFIG_MMC_SDHCI=y
Philipp Tomsichdf23b0d2018-03-26 19:59:08 +0200[diff] [blame]55CONFIG_MMC_SDHCI_SDMA=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]56CONFIG_MMC_SDHCI_ROCKCHIP=y
Hugh Cole-Baker2d338232020-11-22 13:03:46 +0000[diff] [blame]57CONFIG_SF_DEFAULT_BUS=1
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]58CONFIG_SF_DEFAULT_SPEED=20000000
Philipp Tomsichb1c07ff2019-02-03 15:59:23 +0100[diff] [blame]59CONFIG_SPI_FLASH_GIGADEVICE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]60CONFIG_SPI_FLASH_WINBOND=y
61CONFIG_PHY_MICREL=y
Philipp Tomsich87321152017-10-30 14:44:55 +0100[diff] [blame]62CONFIG_PHY_MICREL_KSZ90X1=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]63CONFIG_DM_ETH=y
64CONFIG_ETH_DESIGNWARE=y
65CONFIG_GMAC_ROCKCHIP=y
Heiko Stuebnerf9fb9552020-06-05 12:06:43 +0200[diff] [blame]66CONFIG_PHY_ROCKCHIP_INNO_USB2=y
67CONFIG_PHY_ROCKCHIP_TYPEC=y
Philipp Tomsich3baf4402018-11-30 20:00:09 +0100[diff] [blame]68CONFIG_DM_PMIC_FAN53555=y
Philipp Tomsich222464f2017-05-31 18:18:46 +0200[diff] [blame]69CONFIG_PMIC_RK8XX=y
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]70CONFIG_SPL_DM_REGULATOR=y
Christoph Muellner8356c892019-01-02 15:09:17 +0100[diff] [blame]71CONFIG_REGULATOR_PWM=y
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]72CONFIG_SPL_DM_REGULATOR_FIXED=y
73CONFIG_DM_REGULATOR_GPIO=y
Philipp Tomsich222464f2017-05-31 18:18:46 +0200[diff] [blame]74CONFIG_REGULATOR_RK8XX=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]75CONFIG_PWM_ROCKCHIP=y
Heiko Stuebnerf9fb9552020-06-05 12:06:43 +0200[diff] [blame]76CONFIG_DM_RESET=y
Klaus Gogercda97be2018-04-13 10:54:28 +0200[diff] [blame]77CONFIG_DM_RTC=y
78CONFIG_RTC_ISL1208=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]79CONFIG_DEBUG_UART_SHIFT=2
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]80CONFIG_ROCKCHIP_SPI=y
81CONFIG_SYSRESET=y
82CONFIG_USB=y
83CONFIG_USB_XHCI_HCD=y
84CONFIG_USB_XHCI_DWC3=y
85CONFIG_USB_EHCI_HCD=y
86CONFIG_USB_EHCI_GENERIC=y
Heiko Stuebnerf9fb9552020-06-05 12:06:43 +0200[diff] [blame]87CONFIG_USB_DWC3=y
88CONFIG_USB_DWC3_GENERIC=y
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]89CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]90CONFIG_USB_ETHER_ASIX=y
91CONFIG_USB_ETHER_ASIX88179=y
92CONFIG_USB_ETHER_MCS7830=y
93CONFIG_USB_ETHER_RTL8152=y
94CONFIG_USB_ETHER_SMSC95XX=y
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]95CONFIG_DM_VIDEO=y
Anatolij Gustschindba36702020-02-04 22:43:06 +0100[diff] [blame]96# CONFIG_VIDEO_BPP8 is not set
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]97CONFIG_DISPLAY=y
98CONFIG_VIDEO_ROCKCHIP=y
99CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Patrick Delaunayb1f17632020-09-28 11:30:16 +0200[diff] [blame]100CONFIG_BMP_16BPP=y
101CONFIG_BMP_24BPP=y
102CONFIG_BMP_32BPP=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]103CONFIG_ERRNO_STR=y