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git01.mediatek.com / filogic / uboot / 4f80e28f160d347957b2f2dfda3a59e7c41dfc6f / . / arch / arm / dts / k3-am642-evm-u-boot.dtsi
blob: ee6656774d6bfaa2a8417e1b21963df029a13866 [file] [log] [blame]
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]8/ {
9 chosen {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]10 tick-timer = &main_timer0;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]11 };
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]12};
13
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]14&main_timer0 {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]15 clock-frequency = <200000000>;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]16};
17
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]18&usb0 {
19 dr_mode="peripheral";
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]20};
21
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]22&main_mmc1_pins_default {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]23 bootph-all;
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]24};
25
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]26&dmsc {
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]27 k3_sysreset: sysreset-controller {
28 compatible = "ti,sci-sysreset";
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]29 bootph-all;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]30 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]31};
32
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]33&sdhci0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]34 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]35};
36
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]37&main_mmc1_pins_default {
38 bootph-all;
39};
40
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]41&inta_main_dmss {
42 bootph-all;
43};
44
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]45&main_bcdma {
46 reg = <0x00 0x485c0100 0x00 0x100>,
47 <0x00 0x4c000000 0x00 0x20000>,
48 <0x00 0x4a820000 0x00 0x20000>,
49 <0x00 0x4aa40000 0x00 0x20000>,
50 <0x00 0x4bc00000 0x00 0x100000>,
51 <0x00 0x48600000 0x00 0x8000>,
52 <0x00 0x484a4000 0x00 0x2000>,
53 <0x00 0x484c2000 0x00 0x2000>;
54 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
55 "cfg", "tchan", "rchan";
56};
57
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]58&main_pktdma {
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]59 reg = <0x00 0x485c0000 0x00 0x100>,
60 <0x00 0x4a800000 0x00 0x20000>,
61 <0x00 0x4aa00000 0x00 0x40000>,
62 <0x00 0x4b800000 0x00 0x400000>,
63 <0x00 0x485e0000 0x00 0x20000>,
64 <0x00 0x484a0000 0x00 0x4000>,
65 <0x00 0x484c0000 0x00 0x2000>,
66 <0x00 0x48430000 0x00 0x4000>;
67 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
68 "tchan", "rchan", "rflow";
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]69 bootph-all;
70};
71
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]72&cpsw_port2 {
73 status = "disabled";
74};
Jonathan Humphreyse1ce4f42024-02-23 18:17:02 -0600[diff] [blame]75
76&ospi0_pins_default {
77 bootph-all;
78};
79
80&fss {
81 bootph-all;
82};
83
84&ospi0 {
85 bootph-all;
86
87 flash@0 {
88 bootph-all;
89 };
90};