blob: 00d3eb9ce7a47503f8ca78e8a3cf9709cd3e8341 [file] [log] [blame]
developerb73d7952020-01-10 16:30:26 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
developerb73d7952020-01-10 16:30:26 +08007#include <fdtdec.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
developerb73d7952020-01-10 16:30:26 +08009#include <asm/armv8/mmu.h>
developer87bf1bc2023-07-19 17:15:41 +080010#include <asm/system.h>
11#include <asm/global_data.h>
12#include <asm/u-boot.h>
13#include <linux/sizes.h>
14
15DECLARE_GLOBAL_DATA_PTR;
developerb73d7952020-01-10 16:30:26 +080016
17int print_cpuinfo(void)
18{
19 printf("CPU: MediaTek MT7622\n");
20 return 0;
21}
22
23int dram_init(void)
24{
25 int ret;
26
developer87bf1bc2023-07-19 17:15:41 +080027 ret = fdtdec_setup_mem_size_base();
developerb73d7952020-01-10 16:30:26 +080028 if (ret)
29 return ret;
developerb73d7952020-01-10 16:30:26 +080030
developer87bf1bc2023-07-19 17:15:41 +080031 gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
32
33 return 0;
developerb73d7952020-01-10 16:30:26 +080034}
35
Harald Seiler6f14d5f2020-12-15 16:47:52 +010036void reset_cpu(void)
developerb73d7952020-01-10 16:30:26 +080037{
38 psci_system_reset();
39}
40
41static struct mm_region mt7622_mem_map[] = {
42 {
43 /* DDR */
44 .virt = 0x40000000UL,
45 .phys = 0x40000000UL,
46 .size = 0x40000000UL,
47 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
48 }, {
49 .virt = 0x00000000UL,
50 .phys = 0x00000000UL,
51 .size = 0x40000000UL,
52 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
53 PTE_BLOCK_NON_SHARE |
54 PTE_BLOCK_PXN | PTE_BLOCK_UXN
55 }, {
56 0,
57 }
58};
59struct mm_region *mem_map = mt7622_mem_map;