developer | b73d795 | 2020-01-10 16:30:26 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2019 MediaTek Inc. |
| 4 | * Author: Sam Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
developer | b73d795 | 2020-01-10 16:30:26 +0800 | [diff] [blame] | 7 | #include <fdtdec.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 8 | #include <init.h> |
developer | b73d795 | 2020-01-10 16:30:26 +0800 | [diff] [blame] | 9 | #include <asm/armv8/mmu.h> |
developer | 87bf1bc | 2023-07-19 17:15:41 +0800 | [diff] [blame] | 10 | #include <asm/system.h> |
| 11 | #include <asm/global_data.h> |
| 12 | #include <asm/u-boot.h> |
| 13 | #include <linux/sizes.h> |
| 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
developer | b73d795 | 2020-01-10 16:30:26 +0800 | [diff] [blame] | 16 | |
| 17 | int print_cpuinfo(void) |
| 18 | { |
| 19 | printf("CPU: MediaTek MT7622\n"); |
| 20 | return 0; |
| 21 | } |
| 22 | |
| 23 | int dram_init(void) |
| 24 | { |
| 25 | int ret; |
| 26 | |
developer | 87bf1bc | 2023-07-19 17:15:41 +0800 | [diff] [blame] | 27 | ret = fdtdec_setup_mem_size_base(); |
developer | b73d795 | 2020-01-10 16:30:26 +0800 | [diff] [blame] | 28 | if (ret) |
| 29 | return ret; |
developer | b73d795 | 2020-01-10 16:30:26 +0800 | [diff] [blame] | 30 | |
developer | 87bf1bc | 2023-07-19 17:15:41 +0800 | [diff] [blame] | 31 | gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G); |
| 32 | |
| 33 | return 0; |
developer | b73d795 | 2020-01-10 16:30:26 +0800 | [diff] [blame] | 34 | } |
| 35 | |
Harald Seiler | 6f14d5f | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 36 | void reset_cpu(void) |
developer | b73d795 | 2020-01-10 16:30:26 +0800 | [diff] [blame] | 37 | { |
| 38 | psci_system_reset(); |
| 39 | } |
| 40 | |
| 41 | static struct mm_region mt7622_mem_map[] = { |
| 42 | { |
| 43 | /* DDR */ |
| 44 | .virt = 0x40000000UL, |
| 45 | .phys = 0x40000000UL, |
| 46 | .size = 0x40000000UL, |
| 47 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, |
| 48 | }, { |
| 49 | .virt = 0x00000000UL, |
| 50 | .phys = 0x00000000UL, |
| 51 | .size = 0x40000000UL, |
| 52 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 53 | PTE_BLOCK_NON_SHARE | |
| 54 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 55 | }, { |
| 56 | 0, |
| 57 | } |
| 58 | }; |
| 59 | struct mm_region *mem_map = mt7622_mem_map; |