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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warren80205862011-04-14 12:09:40 +00002/*
3 * Copyright (c) 2011, Google Inc. All rights reserved.
Tom Warrenc570d7a2012-05-22 12:19:25 +00004 * Portions Copyright 2011-2012 NVIDIA Corporation
Tom Warren80205862011-04-14 12:09:40 +00005 */
6
Tom Warrenab371962012-09-19 15:50:56 -07007#ifndef _TEGRA20_GPIO_H_
8#define _TEGRA20_GPIO_H_
Tom Warren80205862011-04-14 12:09:40 +00009
10/*
Tom Warrenb3878b82011-06-17 06:27:28 +000011 * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
Tom Warren80205862011-04-14 12:09:40 +000012 * each with 8 GPIOs.
13 */
Tom Warrenb3878b82011-06-17 06:27:28 +000014#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
15#define TEGRA_GPIO_BANKS 7 /* number of banks */
Tom Warrenab371962012-09-19 15:50:56 -070016
17#include <asm/arch-tegra/gpio.h>
Tom Warren80205862011-04-14 12:09:40 +000018
19/* GPIO Controller registers for a single bank */
20struct gpio_ctlr_bank {
21 uint gpio_config[TEGRA_GPIO_PORTS];
22 uint gpio_dir_out[TEGRA_GPIO_PORTS];
23 uint gpio_out[TEGRA_GPIO_PORTS];
24 uint gpio_in[TEGRA_GPIO_PORTS];
25 uint gpio_int_status[TEGRA_GPIO_PORTS];
26 uint gpio_int_enable[TEGRA_GPIO_PORTS];
27 uint gpio_int_level[TEGRA_GPIO_PORTS];
28 uint gpio_int_clear[TEGRA_GPIO_PORTS];
29};
30
31struct gpio_ctlr {
32 struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
33};
34
Tom Warrenab371962012-09-19 15:50:56 -070035#endif /* TEGRA20_GPIO_H_ */