Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Tom Warren | 8020586 | 2011-04-14 12:09:40 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2011, Google Inc. All rights reserved. |
Tom Warren | c570d7a | 2012-05-22 12:19:25 +0000 | [diff] [blame] | 4 | * Portions Copyright 2011-2012 NVIDIA Corporation |
Tom Warren | 8020586 | 2011-04-14 12:09:40 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Tom Warren | ab37196 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 7 | #ifndef _TEGRA20_GPIO_H_ |
| 8 | #define _TEGRA20_GPIO_H_ |
Tom Warren | 8020586 | 2011-04-14 12:09:40 +0000 | [diff] [blame] | 9 | |
| 10 | /* |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 11 | * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, |
Tom Warren | 8020586 | 2011-04-14 12:09:40 +0000 | [diff] [blame] | 12 | * each with 8 GPIOs. |
| 13 | */ |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 14 | #define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ |
| 15 | #define TEGRA_GPIO_BANKS 7 /* number of banks */ |
Tom Warren | ab37196 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 16 | |
| 17 | #include <asm/arch-tegra/gpio.h> |
Tom Warren | 8020586 | 2011-04-14 12:09:40 +0000 | [diff] [blame] | 18 | |
| 19 | /* GPIO Controller registers for a single bank */ |
| 20 | struct gpio_ctlr_bank { |
| 21 | uint gpio_config[TEGRA_GPIO_PORTS]; |
| 22 | uint gpio_dir_out[TEGRA_GPIO_PORTS]; |
| 23 | uint gpio_out[TEGRA_GPIO_PORTS]; |
| 24 | uint gpio_in[TEGRA_GPIO_PORTS]; |
| 25 | uint gpio_int_status[TEGRA_GPIO_PORTS]; |
| 26 | uint gpio_int_enable[TEGRA_GPIO_PORTS]; |
| 27 | uint gpio_int_level[TEGRA_GPIO_PORTS]; |
| 28 | uint gpio_int_clear[TEGRA_GPIO_PORTS]; |
| 29 | }; |
| 30 | |
| 31 | struct gpio_ctlr { |
| 32 | struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; |
| 33 | }; |
| 34 | |
Tom Warren | ab37196 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 35 | #endif /* TEGRA20_GPIO_H_ */ |