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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +05302/*
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on davinci_dvevm.h. Original Copyrights follow:
6 *
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +05308 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * Board
15 */
Ben Gardiner4b9538a2010-10-14 17:26:29 -040016#define CONFIG_DRIVER_TI_EMAC
Lad, Prabhakarc618b612012-06-24 21:35:23 +000017/* check if direct NOR boot config is used */
18#ifndef CONFIG_DIRECT_NOR_BOOT
Stefano Babicfc850ab2010-11-11 15:38:02 +010019#define CONFIG_USE_SPIFLASH
Lad, Prabhakarc618b612012-06-24 21:35:23 +000020#endif
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053021
22/*
Adam Ford5ff6c0a2017-09-17 20:43:46 -050023* Disable DM_* for SPL build and can be re-enabled after adding
24* DM support in SPL
25*/
26#ifdef CONFIG_SPL_BUILD
27#undef CONFIG_DM_SPI
28#undef CONFIG_DM_SPI_FLASH
29#undef CONFIG_DM_I2C
30#undef CONFIG_DM_I2C_COMPAT
31#endif
32/*
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053033 * SoC Configuration
34 */
Christian Riesch48c2d6d2012-02-02 00:44:39 +000035#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053036#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
37#define CONFIG_SYS_OSCIN_FREQ 24000000
38#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
39#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053040
Lad, Prabhakarc618b612012-06-24 21:35:23 +000041#ifdef CONFIG_DIRECT_NOR_BOOT
42#define CONFIG_ARCH_CPU_INIT
Lad, Prabhakarc618b612012-06-24 21:35:23 +000043#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
Lad, Prabhakarc618b612012-06-24 21:35:23 +000044#endif
45
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053046/*
47 * Memory Info
48 */
49#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053050#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
51#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
Ben Gardiner7618f612010-08-23 09:08:15 -040052#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053053
54/* memtest start addr */
55#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
56
57/* memtest will be run on 16MB */
58#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
59
60#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053061
Christian Riesch63e341b2011-12-09 09:47:37 +000062#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
63 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
64 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
65 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
66 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
67 DAVINCI_SYSCFG_SUSPSRC_I2C)
68
69/*
70 * PLL configuration
71 */
Christian Riesch63e341b2011-12-09 09:47:37 +000072
73#define CONFIG_SYS_DA850_PLL0_PLLM 24
74#define CONFIG_SYS_DA850_PLL1_PLLM 21
75
76/*
77 * DDR2 memory configuration
78 */
79#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
80 DV_DDR_PHY_EXT_STRBEN | \
81 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
82
83#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
84 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
85 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
86 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
87 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
88 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
89 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
90 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
91
92/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
93#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
94
95#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
96 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
97 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
98 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
99 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
100 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
101 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
102 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
103 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
104
105#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
106 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
107 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
108 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
109 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
110 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
111 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
112 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
113
114#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
115#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
116
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530117/*
118 * Serial Driver info
119 */
Adam Ford5ff6c0a2017-09-17 20:43:46 -0500120
121#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530122#define CONFIG_SYS_NS16550_SERIAL
123#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
124#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
Adam Ford5ff6c0a2017-09-17 20:43:46 -0500125#endif
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530126#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530127
Stefano Babicfc850ab2010-11-11 15:38:02 +0100128#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
Adam Ford5ff6c0a2017-09-17 20:43:46 -0500129#ifdef CONFIG_SPL_BUILD
130#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
Stefano Babicfc850ab2010-11-11 15:38:02 +0100131#define CONFIG_SF_DEFAULT_SPEED 30000000
132#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
Adam Ford5ff6c0a2017-09-17 20:43:46 -0500133#endif
Stefano Babicfc850ab2010-11-11 15:38:02 +0100134
Lad, Prabhakara52e2602012-06-24 21:35:19 +0000135#ifdef CONFIG_USE_SPIFLASH
Lad, Prabhakara52e2602012-06-24 21:35:19 +0000136#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
Peter Howardb521c262014-12-17 12:14:36 +1100137#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
Lad, Prabhakara52e2602012-06-24 21:35:19 +0000138#endif
139
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530140/*
141 * I2C Configuration
142 */
Adam Ford66017122017-09-17 20:43:48 -0500143#ifndef CONFIG_SPL_BUILD
Vitaly Andrianovbc9cd952014-04-04 13:16:52 -0400144#define CONFIG_SYS_I2C_DAVINCI
Sudhakar Rajashekhara5851e122010-11-18 09:59:37 -0500145#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
Adam Ford66017122017-09-17 20:43:48 -0500146#endif
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530147
148/*
Ben Gardiner314305c2010-10-14 17:26:25 -0400149 * Flash & Environment
150 */
Adam Fordfc3ad5b2018-07-10 06:47:33 -0500151#ifdef CONFIG_NAND
Ben Gardiner314305c2010-10-14 17:26:25 -0400152#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
153#define CONFIG_ENV_SIZE (128 << 10)
154#define CONFIG_SYS_NAND_USE_FLASH_BBT
155#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
156#define CONFIG_SYS_NAND_PAGE_2K
157#define CONFIG_SYS_NAND_CS 3
158#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Eric Benardf7dafcf2013-04-22 05:55:00 +0000159#define CONFIG_SYS_NAND_MASK_CLE 0x10
160#define CONFIG_SYS_NAND_MASK_ALE 0x8
Ben Gardiner314305c2010-10-14 17:26:25 -0400161#undef CONFIG_SYS_NAND_HW_ECC
162#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Lad, Prabhakaref160a32012-06-24 21:35:22 +0000163#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
164#define CONFIG_SYS_NAND_5_ADDR_CYCLE
165#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
166#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
167#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
168#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
169#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
170#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
171#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
172 CONFIG_SYS_NAND_U_BOOT_SIZE - \
173 CONFIG_SYS_MALLOC_LEN - \
174 GENERATED_GBL_DATA_SIZE)
175#define CONFIG_SYS_NAND_ECCPOS { \
176 24, 25, 26, 27, 28, \
177 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
178 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
179 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
180 59, 60, 61, 62, 63 }
181#define CONFIG_SYS_NAND_PAGE_COUNT 64
182#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
183#define CONFIG_SYS_NAND_ECCSIZE 512
184#define CONFIG_SYS_NAND_ECCBYTES 10
185#define CONFIG_SYS_NAND_OOBSIZE 64
Scott Woodc352a0c2012-09-20 19:09:07 -0500186#define CONFIG_SPL_NAND_BASE
187#define CONFIG_SPL_NAND_DRIVERS
188#define CONFIG_SPL_NAND_ECC
Lad, Prabhakaref160a32012-06-24 21:35:22 +0000189#define CONFIG_SPL_NAND_LOAD
Ben Gardiner314305c2010-10-14 17:26:25 -0400190#endif
191
192/*
Ben Gardiner4b9538a2010-10-14 17:26:29 -0400193 * Network & Ethernet Configuration
194 */
195#ifdef CONFIG_DRIVER_TI_EMAC
Ben Gardiner4b9538a2010-10-14 17:26:29 -0400196#define CONFIG_MII
Ben Gardiner4b9538a2010-10-14 17:26:29 -0400197#define CONFIG_BOOTP_DNS2
198#define CONFIG_BOOTP_SEND_HOSTNAME
199#define CONFIG_NET_RETRY_COUNT 10
Ben Gardiner4b9538a2010-10-14 17:26:29 -0400200#endif
201
Nagabhushana Netagunte87539bf2011-09-03 22:18:32 -0400202#ifdef CONFIG_USE_NOR
Nagabhushana Netagunte87539bf2011-09-03 22:18:32 -0400203#define CONFIG_FLASH_CFI_DRIVER
204#define CONFIG_SYS_FLASH_CFI
205#define CONFIG_SYS_FLASH_PROTECTION
206#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
207#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
208#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
209#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
210#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
211#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
212#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
213 + 3)
214#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
215#endif
216
Stefano Babicfc850ab2010-11-11 15:38:02 +0100217#ifdef CONFIG_USE_SPIFLASH
Stefano Babicfc850ab2010-11-11 15:38:02 +0100218#define CONFIG_ENV_SIZE (64 << 10)
Peter Howardb521c262014-12-17 12:14:36 +1100219#define CONFIG_ENV_OFFSET (512 << 10)
Stefano Babicfc850ab2010-11-11 15:38:02 +0100220#define CONFIG_ENV_SECT_SIZE (64 << 10)
Adam Ford4c9c7232017-09-17 20:43:47 -0500221#ifdef CONFIG_SPL_BUILD
222#undef CONFIG_SPI_FLASH_MTD
223#endif
Stefano Babicfc850ab2010-11-11 15:38:02 +0100224#endif
225
Ben Gardiner4b9538a2010-10-14 17:26:29 -0400226/*
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530227 * U-Boot general configuration
228 */
Nagabhushana Netagunte24d30962011-09-03 22:19:28 -0400229#define CONFIG_MISC_INIT_R
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530230#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530231#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530232#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
233#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530234#define CONFIG_MX_CYCLIC
235
236/*
237 * Linux Information
238 */
Ben Gardiner14c2f7e2010-10-14 17:26:32 -0400239#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
Nagabhushana Netagunte24d30962011-09-03 22:19:28 -0400240#define CONFIG_HWCONFIG /* enable hwconfig */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530241#define CONFIG_CMDLINE_TAG
Sekhar Nori6e112202010-11-19 11:39:48 -0500242#define CONFIG_REVISION_TAG
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530243#define CONFIG_SETUP_MEMORY_TAGS
Adam Ford5ff6c0a2017-09-17 20:43:46 -0500244
245#define CONFIG_BOOTCOMMAND \
246 "run envboot; " \
247 "run mmcboot; "
248
249#define DEFAULT_LINUX_BOOT_ENV \
250 "loadaddr=0xc0700000\0" \
251 "fdtaddr=0xc0600000\0" \
252 "scriptaddr=0xc0600000\0"
253
254#include <environment/ti/mmc.h>
255
256#define CONFIG_EXTRA_ENV_SETTINGS \
257 DEFAULT_LINUX_BOOT_ENV \
258 DEFAULT_MMC_TI_ARGS \
259 "bootpart=0:2\0" \
260 "bootdir=/boot\0" \
261 "bootfile=zImage\0" \
262 "fdtfile=da850-evm.dtb\0" \
263 "boot_fdt=yes\0" \
264 "boot_fit=0\0" \
265 "console=ttyS2,115200n8\0" \
266 "hwconfig=dsp:wake=yes"
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530267
Hadli, Manjunath0dfccbe2012-02-06 00:30:44 +0000268#ifdef CONFIG_CMD_BDI
269#define CONFIG_CLOCKS
270#endif
271
Adam Fordfc3ad5b2018-07-10 06:47:33 -0500272#if !defined(CONFIG_NAND) && \
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530273 !defined(CONFIG_USE_NOR) && \
274 !defined(CONFIG_USE_SPIFLASH)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530275#define CONFIG_ENV_SIZE (16 << 10)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530276#endif
277
Lad, Prabhakarc618b612012-06-24 21:35:23 +0000278#ifndef CONFIG_DIRECT_NOR_BOOT
Christian Riesch63e341b2011-12-09 09:47:37 +0000279/* defines for SPL */
Tom Rini12938582012-08-14 12:27:13 -0700280#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
281 CONFIG_SYS_MALLOC_LEN)
282#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Christian Riesch63e341b2011-12-09 09:47:37 +0000283#define CONFIG_SPL_STACK 0x8001ff00
284#define CONFIG_SPL_TEXT_BASE 0x80000000
Albert ARIBAUDa02e3cc2013-04-12 05:14:32 +0000285#define CONFIG_SPL_MAX_FOOTPRINT 32768
Christian Riesch40aad402014-05-07 10:16:28 +0200286#define CONFIG_SPL_PAD_TO 32768
Lad, Prabhakarc618b612012-06-24 21:35:23 +0000287#endif
Lad, Prabhakar8dc6df82012-06-24 21:35:20 +0000288
289/* Load U-Boot Image From MMC */
Lad, Prabhakar8dc6df82012-06-24 21:35:20 +0000290
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200291/* additions for new relocation code, must added to all boards */
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200292#define CONFIG_SYS_SDRAM_BASE 0xc0000000
Lad, Prabhakarc618b612012-06-24 21:35:23 +0000293
294#ifdef CONFIG_DIRECT_NOR_BOOT
295#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
296#else
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200297#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200298 GENERATED_GBL_DATA_SIZE)
Lad, Prabhakarc618b612012-06-24 21:35:23 +0000299#endif /* CONFIG_DIRECT_NOR_BOOT */
Simon Glassce3574f2017-05-17 08:23:09 -0600300
301#include <asm/arch/hardware.h>
302
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530303#endif /* __CONFIG_H */