Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 2 | /* |
Albert ARIBAUD | 340983d | 2011-04-22 19:41:02 +0200 | [diff] [blame] | 3 | * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 4 | * |
| 5 | * Based on original Kirkwood support which is |
| 6 | * (C) Copyright 2009 |
| 7 | * Marvell Semiconductor <www.marvell.com> |
| 8 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef _CONFIG_EDMINIV2_H |
| 12 | #define _CONFIG_EDMINIV2_H |
| 13 | |
| 14 | /* |
Albert ARIBAUD | 2ac3792 | 2015-01-31 22:55:38 +0100 | [diff] [blame] | 15 | * SPL |
| 16 | */ |
| 17 | |
Albert ARIBAUD | 2ac3792 | 2015-01-31 22:55:38 +0100 | [diff] [blame] | 18 | #define CONFIG_SYS_UBOOT_BASE 0xfff90000 |
| 19 | #define CONFIG_SYS_UBOOT_START 0x00800000 |
Albert ARIBAUD | 2ac3792 | 2015-01-31 22:55:38 +0100 | [diff] [blame] | 20 | |
| 21 | /* |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 22 | * High Level Configuration Options (easy to change) |
| 23 | */ |
| 24 | |
Lei Wen | 749941a | 2011-10-24 16:27:32 +0000 | [diff] [blame] | 25 | #include <asm/arch/orion5x.h> |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 26 | /* |
| 27 | * CLKs configurations |
| 28 | */ |
| 29 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 30 | /* |
| 31 | * Board-specific values for Orion5x MPP low level init: |
| 32 | * - MPPs 12 to 15 are SATA LEDs (mode 5) |
| 33 | * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for |
| 34 | * MPP16 to MPP19, mode 0 for others |
| 35 | */ |
| 36 | |
| 37 | #define ORION5X_MPP0_7 0x00000003 |
| 38 | #define ORION5X_MPP8_15 0x55550000 |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 39 | #define ORION5X_MPP16_23 0x00005555 |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 40 | |
| 41 | /* |
| 42 | * Board-specific values for Orion5x GPIO low level init: |
| 43 | * - GPIO3 is input (RTC interrupt) |
| 44 | * - GPIO16 is Power LED control (0 = on, 1 = off) |
| 45 | * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) |
| 46 | * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) |
Albert ARIBAUD | dea1cfb | 2012-08-16 06:35:21 +0000 | [diff] [blame] | 47 | * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) |
| 48 | * - GPIO22 is SATA disk power status () |
| 49 | * - GPIO23 is supply status for SATA disk () |
| 50 | * - GPIO24 is supply control for board (write 1 to power off) |
| 51 | * Last GPIO is 25, further bits are supposed to be 0. |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 52 | * Enable mask has ones for INPUT, 0 for OUTPUT. |
Albert ARIBAUD | dea1cfb | 2012-08-16 06:35:21 +0000 | [diff] [blame] | 53 | * Default is LED ON, board ON :) |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 54 | */ |
| 55 | |
Albert ARIBAUD | dea1cfb | 2012-08-16 06:35:21 +0000 | [diff] [blame] | 56 | #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca |
| 57 | #define ORION5X_GPIO_OUT_VALUE 0x00000000 |
| 58 | #define ORION5X_GPIO_IN_POLARITY 0x000000d0 |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 59 | |
| 60 | /* |
| 61 | * NS16550 Configuration |
| 62 | */ |
| 63 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 64 | #define CONFIG_SYS_NS16550_SERIAL |
| 65 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 66 | #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK |
| 67 | #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE |
| 68 | |
| 69 | /* |
| 70 | * Serial Port configuration |
| 71 | * The following definitions let you select what serial you want to use |
| 72 | * for your console driver. |
| 73 | */ |
| 74 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 75 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 76 | { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } |
| 77 | |
| 78 | /* |
| 79 | * FLASH configuration |
| 80 | */ |
| 81 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 82 | #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ |
| 83 | #define CONFIG_SYS_FLASH_BASE 0xfff80000 |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 84 | |
| 85 | /* auto boot */ |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 86 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 87 | /* |
Albert Aribaud | c5b205b | 2010-07-12 22:24:30 +0200 | [diff] [blame] | 88 | * Network |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 89 | */ |
Albert Aribaud | c5b205b | 2010-07-12 22:24:30 +0200 | [diff] [blame] | 90 | |
| 91 | #ifdef CONFIG_CMD_NET |
Albert Aribaud | c5b205b | 2010-07-12 22:24:30 +0200 | [diff] [blame] | 92 | #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ |
| 93 | #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ |
| 94 | #define CONFIG_PHY_BASE_ADR 0x8 |
Albert Aribaud | c5b205b | 2010-07-12 22:24:30 +0200 | [diff] [blame] | 95 | #endif |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 96 | |
| 97 | /* |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 98 | * IDE |
| 99 | */ |
Simon Glass | b569a01 | 2017-05-17 03:25:30 -0600 | [diff] [blame] | 100 | #ifdef CONFIG_IDE |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 101 | #define __io |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 102 | /* Data, registers and alternate blocks are at the same offset */ |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 103 | /* Each 8-bit ATA register is aligned to a 4-bytes address */ |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 104 | /* Controller supports 48-bits LBA addressing */ |
| 105 | #define CONFIG_LBA48 |
| 106 | /* A single bus, a single device */ |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 107 | /* ATA registers base is at SATA controller base */ |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 108 | /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 109 | /* end of IDE defines */ |
| 110 | #endif /* CMD_IDE */ |
| 111 | |
| 112 | /* |
Albert ARIBAUD | 90bdece | 2012-01-15 22:08:41 +0000 | [diff] [blame] | 113 | * Common USB/EHCI configuration |
| 114 | */ |
| 115 | #ifdef CONFIG_CMD_USB |
Albert ARIBAUD | 90bdece | 2012-01-15 22:08:41 +0000 | [diff] [blame] | 116 | #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE |
Albert ARIBAUD | 90bdece | 2012-01-15 22:08:41 +0000 | [diff] [blame] | 117 | #endif /* CONFIG_CMD_USB */ |
| 118 | |
| 119 | /* |
Albert Aribaud | 81c9981 | 2010-08-27 18:26:06 +0200 | [diff] [blame] | 120 | * I2C related stuff |
| 121 | */ |
| 122 | #ifdef CONFIG_CMD_I2C |
Paul Kocialkowski | 2fae3e7 | 2015-04-10 23:09:51 +0200 | [diff] [blame] | 123 | #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE |
Albert Aribaud | 81c9981 | 2010-08-27 18:26:06 +0200 | [diff] [blame] | 124 | #endif |
| 125 | |
| 126 | /* |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 127 | * Environment variables configurations |
| 128 | */ |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 129 | |
Albert ARIBAUD | c4d48a6 | 2012-02-06 20:32:19 +0530 | [diff] [blame] | 130 | /* Enable command line editing */ |
Albert ARIBAUD | c4d48a6 | 2012-02-06 20:32:19 +0530 | [diff] [blame] | 131 | |
| 132 | /* provide extensive help */ |
Albert ARIBAUD | c4d48a6 | 2012-02-06 20:32:19 +0530 | [diff] [blame] | 133 | |
Albert Aribaud | a2ddee4 | 2010-10-11 13:13:29 +0200 | [diff] [blame] | 134 | /* additions for new relocation code, must be added to all boards */ |
| 135 | #define CONFIG_SYS_SDRAM_BASE 0 |
Albert Aribaud | a2ddee4 | 2010-10-11 13:13:29 +0200 | [diff] [blame] | 136 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 137 | #endif /* _CONFIG_EDMINIV2_H */ |