blob: 8ee3adc8058491a4ca1bda0057b1feef0f5a104a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Eddy Petrișor5178dc12016-06-05 03:43:00 +03002/*
3 * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
Eddy Petrișor5178dc12016-06-05 03:43:00 +03004 */
5
6#include <common.h>
Simon Glass33d1e702019-11-14 12:57:32 -07007#include <cpu_func.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -06009#include <asm/cache.h>
Eddy Petrișor5178dc12016-06-05 03:43:00 +030010#include <asm/io.h>
11#include <asm/system.h>
12#include <asm/armv8/mmu.h>
13#include <asm/io.h>
14#include <asm/arch/mc_me_regs.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060015#include <linux/bitops.h>
Eddy Petrișor5178dc12016-06-05 03:43:00 +030016#include "cpu.h"
17
Eddy Petrișor5178dc12016-06-05 03:43:00 +030018u32 cpu_mask(void)
19{
20 return readl(MC_ME_CS);
21}
22
Trevor Woerner43ec7e02019-05-03 09:41:00 -040023#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
Eddy Petrișor5178dc12016-06-05 03:43:00 +030024
25#define S32V234_IRAM_BASE 0x3e800000UL
26#define S32V234_IRAM_SIZE 0x800000UL
27#define S32V234_DRAM_BASE1 0x80000000UL
28#define S32V234_DRAM_SIZE1 0x40000000UL
29#define S32V234_DRAM_BASE2 0xC0000000UL
30#define S32V234_DRAM_SIZE2 0x20000000UL
31#define S32V234_PERIPH_BASE 0x40000000UL
32#define S32V234_PERIPH_SIZE 0x40000000UL
33
34static struct mm_region s32v234_mem_map[] = {
35 {
York Sunc7104e52016-06-24 16:46:22 -070036 .virt = S32V234_IRAM_BASE,
37 .phys = S32V234_IRAM_BASE,
Eddy Petrișor5178dc12016-06-05 03:43:00 +030038 .size = S32V234_IRAM_SIZE,
39 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
40 PTE_BLOCK_OUTER_SHARE
41 }, {
York Sunc7104e52016-06-24 16:46:22 -070042 .virt = S32V234_DRAM_BASE1,
43 .phys = S32V234_DRAM_BASE1,
Eddy Petrișor5178dc12016-06-05 03:43:00 +030044 .size = S32V234_DRAM_SIZE1,
45 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
46 PTE_BLOCK_OUTER_SHARE
47 }, {
York Sunc7104e52016-06-24 16:46:22 -070048 .virt = S32V234_PERIPH_BASE,
49 .phys = S32V234_PERIPH_BASE,
Eddy Petrișor5178dc12016-06-05 03:43:00 +030050 .size = S32V234_PERIPH_SIZE,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
52 PTE_BLOCK_NON_SHARE
53 /* TODO: Do we need these? */
54 /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
55 }, {
York Sunc7104e52016-06-24 16:46:22 -070056 .virt = S32V234_DRAM_BASE2,
57 .phys = S32V234_DRAM_BASE2,
Eddy Petrișor5178dc12016-06-05 03:43:00 +030058 .size = S32V234_DRAM_SIZE2,
59 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
60 PTE_BLOCK_OUTER_SHARE
61 }, {
62 /* List terminator */
63 0,
64 }
65};
66
67struct mm_region *mem_map = s32v234_mem_map;
68
69#endif
70
71/*
72 * Return the number of cores on this SOC.
73 */
74int cpu_numcores(void)
75{
76 int numcores;
77 u32 mask;
78
79 mask = cpu_mask();
80 numcores = hweight32(cpu_mask());
81
82 /* Verify if M4 is deactivated */
83 if (mask & 0x1)
84 numcores--;
85
86 return numcores;
87}
88
89#if defined(CONFIG_ARCH_EARLY_INIT_R)
90int arch_early_init_r(void)
91{
92 int rv;
93 asm volatile ("dsb sy");
94 rv = fsl_s32v234_wake_seconday_cores();
95
96 if (rv)
97 printf("Did not wake secondary cores\n");
98
99 asm volatile ("sev");
100 return 0;
101}
102#endif /* CONFIG_ARCH_EARLY_INIT_R */