Blame - arch/arm/mach-socfpga/Kconfig - filogic/uboot

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Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Dalon Westergreen	8d770f4	2017-02-10 17:15:34 -0800	[diff] [blame]	3	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
				4	default 0xa2
				5
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	6	config TARGET_SOCFPGA_ARRIA5
				7	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	8	select TARGET_SOCFPGA_GEN5
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	9
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	10	config TARGET_SOCFPGA_ARRIA10
				11	bool
Ley Foon Tan	48fcc4a	2017-05-03 17:13:32 +0800	[diff] [blame]	12	select SPL_BOARD_INIT if SPL
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	13
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	14	config TARGET_SOCFPGA_CYCLONE5
				15	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	16	select TARGET_SOCFPGA_GEN5
				17
				18	config TARGET_SOCFPGA_GEN5
				19	bool
Ley Foon Tan	016539e	2017-04-05 17:32:51 +0800	[diff] [blame]	20	select ALTERA_SDRAM
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	21
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	22	choice
				23	prompt "Altera SOCFPGA board select"
Joe Hershberger	f069960	2015-05-12 14:46:23 -0500	[diff] [blame]	24	optional
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	25
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	26	config TARGET_SOCFPGA_ARRIA10_SOCDK
				27	bool "Altera SOCFPGA SoCDK (Arria 10)"
				28	select TARGET_SOCFPGA_ARRIA10
				29
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	30	config TARGET_SOCFPGA_ARRIA5_SOCDK
				31	bool "Altera SOCFPGA SoCDK (Arria V)"
				32	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	33
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	34	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				35	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				36	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	37
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	38	config TARGET_SOCFPGA_ARIES_MCVEVK
				39	bool "Aries MCVEVK (Cyclone V)"
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	40	select TARGET_SOCFPGA_CYCLONE5
				41
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	42	config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
				43	bool "Devboards DBM-SoC1 (Cyclone V)"
				44	select TARGET_SOCFPGA_CYCLONE5
				45
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	46	config TARGET_SOCFPGA_EBV_SOCRATES
				47	bool "EBV SoCrates (Cyclone V)"
				48	select TARGET_SOCFPGA_CYCLONE5
				49
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	50	config TARGET_SOCFPGA_IS1
				51	bool "IS1 (Cyclone V)"
				52	select TARGET_SOCFPGA_CYCLONE5
				53
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	54	config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
				55	bool "samtec VIN\|ING FPGA (Cyclone V)"
Tom Rini	22d567e	2017-01-22 19:43:11 -0500	[diff] [blame]	56	select BOARD_LATE_INIT
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	57	select TARGET_SOCFPGA_CYCLONE5
				58
Marek Vasut	2e717ec	2016-06-08 02:57:05 +0200	[diff] [blame]	59	config TARGET_SOCFPGA_SR1500
				60	bool "SR1500 (Cyclone V)"
				61	select TARGET_SOCFPGA_CYCLONE5
				62
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	63	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				64	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				65	select TARGET_SOCFPGA_CYCLONE5
				66
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	67	config TARGET_SOCFPGA_TERASIC_DE10_NANO
				68	bool "Terasic DE10-Nano (Cyclone V)"
				69	select TARGET_SOCFPGA_CYCLONE5
				70
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	71	config TARGET_SOCFPGA_TERASIC_DE1_SOC
				72	bool "Terasic DE1-SoC (Cyclone V)"
				73	select TARGET_SOCFPGA_CYCLONE5
				74
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	75	config TARGET_SOCFPGA_TERASIC_SOCKIT
				76	bool "Terasic SoCkit (Cyclone V)"
				77	select TARGET_SOCFPGA_CYCLONE5
				78
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	79	endchoice
				80
				81	config SYS_BOARD
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	82	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	83	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	84	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	85	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	86	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	87	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	88	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	89	default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	90	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	91	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	92	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	93	default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	94	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	95
				96	config SYS_VENDOR
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	97	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	98	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	99	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	100	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	101	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	102	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	103	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	104	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	105	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	106	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	107	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	108
				109	config SYS_SOC
				110	default "socfpga"
				111
				112	config SYS_CONFIG_NAME
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	113	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	114	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	115	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	116	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	117	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	118	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	119	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	120	default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	121	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	122	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	123	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	124	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	125	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	126
				127	endif