blob: bae10271844add321ed488950d51ecba93449fae [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
maxims@google.com899b40f2017-01-18 13:44:57 -08002/*
3 * Copyright (c) 2016 Google, Inc
maxims@google.com899b40f2017-01-18 13:44:57 -08004 */
5#include <common.h>
6#include <dm.h>
Simon Glass97589732020-05-10 11:40:02 -06007#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
maxims@google.com899b40f2017-01-18 13:44:57 -08009#include <ram.h>
10#include <timer.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060011#include <asm/global_data.h>
maxims@google.com899b40f2017-01-18 13:44:57 -080012#include <asm/io.h>
13#include <asm/arch/timer.h>
14#include <asm/arch/wdt.h>
15#include <linux/err.h>
16#include <dm/uclass.h>
17
18/*
19 * Second Watchdog Timer by default is configured
20 * to trigger secondary boot source.
21 */
22#define AST_2ND_BOOT_WDT 1
23
24/*
25 * Third Watchdog Timer by default is configured
26 * to toggle Flash address mode switch before reset.
27 */
28#define AST_FLASH_ADDR_DETECT_WDT 2
29
30DECLARE_GLOBAL_DATA_PTR;
31
maxims@google.com899b40f2017-01-18 13:44:57 -080032int board_init(void)
33{
Tom Rinibb4dd962022-11-16 13:10:37 -050034 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
maxims@google.com899b40f2017-01-18 13:44:57 -080035
36 return 0;
37}
38
39int dram_init(void)
40{
41 struct udevice *dev;
42 struct ram_info ram;
43 int ret;
44
45 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
46 if (ret) {
47 debug("DRAM FAIL1\r\n");
48 return ret;
49 }
50
51 ret = ram_get_info(dev, &ram);
52 if (ret) {
53 debug("DRAM FAIL2\r\n");
54 return ret;
55 }
56
57 gd->ram_size = ram.size;
58
59 return 0;
60}