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Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04001/*
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +00002 * Common configuration settings for IGEP technology based boards
3 *
4 * (C) Copyright 2012
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04005 * ISEE 2007 SL, <www.iseebcn.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04008 */
9
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +000010#ifndef __IGEP00X0_H
11#define __IGEP00X0_H
12
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040013#include <asm/sizes.h>
14
15/*
16 * High Level Configuration Options
17 */
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040018#define CONFIG_OMAP 1 /* in a TI OMAP core */
19#define CONFIG_OMAP34XX 1 /* which is a 34XX */
Marek Vasutaede1882012-07-21 05:02:23 +000020#define CONFIG_OMAP_GPIO
Lokesh Vutla56055052013-07-30 11:36:30 +053021#define CONFIG_OMAP_COMMON
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040022
23#define CONFIG_SDRC /* The chip has SDRC controller */
24
25#include <asm/arch/cpu.h>
26#include <asm/arch/omap3.h>
Enric Balletbo i Serra74fea922013-02-07 00:40:05 +000027#include <asm/mach-types.h>
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040028
29/*
30 * Display CPU and Board information
31 */
32#define CONFIG_DISPLAY_CPUINFO 1
33#define CONFIG_DISPLAY_BOARDINFO 1
34
35/* Clock Defines */
36#define V_OSCK 26000000 /* Clock output from T2 */
37#define V_SCLK (V_OSCK >> 1)
38
39#define CONFIG_MISC_INIT_R
40
41#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42#define CONFIG_SETUP_MEMORY_TAGS 1
43#define CONFIG_INITRD_TAG 1
44#define CONFIG_REVISION_TAG 1
45
Enric Balletbo i Serra2c2dc652013-03-15 02:32:35 +000046#define CONFIG_OF_LIBFDT
47#define CONFIG_CMD_BOOTZ
Grant Likely100b8492011-03-28 09:59:07 +000048
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040049/*
50 * NS16550 Configuration
51 */
52
53#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
54
55#define CONFIG_SYS_NS16550
56#define CONFIG_SYS_NS16550_SERIAL
57#define CONFIG_SYS_NS16550_REG_SIZE (-4)
58#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
59
60/* select serial console configuration */
61#define CONFIG_CONS_INDEX 3
62#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
63#define CONFIG_SERIAL3 3
64
65/* allow to overwrite serial and ethaddr */
66#define CONFIG_ENV_OVERWRITE
67#define CONFIG_BAUDRATE 115200
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +000068#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
69 115200}
Enric Balletbo i Serrada898a92010-11-04 15:34:33 -040070#define CONFIG_GENERIC_MMC 1
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040071#define CONFIG_MMC 1
Enric Balletbo i Serrada898a92010-11-04 15:34:33 -040072#define CONFIG_OMAP_HSMMC 1
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040073#define CONFIG_DOS_PARTITION 1
74
Javier Martinez Canillasd549ace2012-12-27 03:36:01 +000075/* define to enable boot progress via leds */
Enric Balletbo i Serra02043a72013-02-07 00:40:06 +000076#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
77 (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
Javier Martinez Canillasd549ace2012-12-27 03:36:01 +000078#define CONFIG_SHOW_BOOT_PROGRESS
Enric Balletbo i Serra02043a72013-02-07 00:40:06 +000079#endif
Javier Martinez Canillasd549ace2012-12-27 03:36:01 +000080
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040081/* USB */
82#define CONFIG_MUSB_UDC 1
83#define CONFIG_USB_OMAP3 1
84#define CONFIG_TWL4030_USB 1
85
86/* USB device configuration */
87#define CONFIG_USB_DEVICE 1
88#define CONFIG_USB_TTY 1
89#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
90
91/* Change these to suit your needs */
92#define CONFIG_USBD_VENDORID 0x0451
93#define CONFIG_USBD_PRODUCTID 0x5678
94#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
95#define CONFIG_USBD_PRODUCT_NAME "IGEP"
96
97/* commands to include */
98#include <config_cmd_default.h>
99
100#define CONFIG_CMD_CACHE
Enric Balletbo i Serracffccee2013-08-07 17:53:18 +0200101#define CONFIG_CMD_EXT4
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400102#define CONFIG_CMD_FAT /* FAT support */
Enric Balletbo i Serracffccee2013-08-07 17:53:18 +0200103#define CONFIG_CMD_FS_GENERIC
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400104#define CONFIG_CMD_I2C /* I2C serial bus support */
105#define CONFIG_CMD_MMC /* MMC support */
Javier Martinez Canillas758b7c62012-07-28 01:19:32 +0000106#ifdef CONFIG_BOOT_ONENAND
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400107#define CONFIG_CMD_ONENAND /* ONENAND support */
Javier Martinez Canillas758b7c62012-07-28 01:19:32 +0000108#endif
109#ifdef CONFIG_BOOT_NAND
110#define CONFIG_CMD_NAND
111#endif
Enric Balletbo i Serra02043a72013-02-07 00:40:06 +0000112#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
113 (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400114#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
Javier Martinez Canillase9b14522012-12-27 01:35:56 +0000115#endif
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400116#define CONFIG_CMD_DHCP
117#define CONFIG_CMD_PING
118#define CONFIG_CMD_NFS /* NFS support */
119#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
120#define CONFIG_MTD_DEVICE
121
122#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
123#undef CONFIG_CMD_IMLS /* List all found images */
124
125#define CONFIG_SYS_NO_FLASH
126#define CONFIG_HARD_I2C 1
127#define CONFIG_SYS_I2C_SPEED 100000
128#define CONFIG_SYS_I2C_SLAVE 1
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400129#define CONFIG_DRIVER_OMAP34XX_I2C 1
130
131/*
132 * TWL4030
133 */
134#define CONFIG_TWL4030_POWER 1
135
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400136#define CONFIG_BOOTDELAY 3
137
138#define CONFIG_EXTRA_ENV_SETTINGS \
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -0400139 "usbtty=cdc_acm\0" \
140 "loadaddr=0x82000000\0" \
Javier Martinez Canillas7a0155e2013-08-07 17:53:19 +0200141 "dtbaddr=0x81600000\0" \
142 "bootdir=/boot\0" \
143 "bootfile=zImage\0" \
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -0400144 "usbtty=cdc_acm\0" \
Javier Martinez Canillasdf32d2c2012-06-29 02:45:40 +0000145 "console=ttyO2,115200n8\0" \
Enric Balletbo i Serra52ac7ac2012-04-25 02:34:31 +0000146 "mpurate=auto\0" \
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -0400147 "vram=12M\0" \
148 "dvimode=1024x768MR-16@60\0" \
149 "defaultdisplay=dvi\0" \
150 "mmcdev=0\0" \
151 "mmcroot=/dev/mmcblk0p2 rw\0" \
Javier Martinez Canillasc5d6fb22012-06-29 02:45:41 +0000152 "mmcrootfstype=ext4 rootwait\0" \
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -0400153 "nandroot=/dev/mtdblock4 rw\0" \
154 "nandrootfstype=jffs2\0" \
155 "mmcargs=setenv bootargs console=${console} " \
156 "mpurate=${mpurate} " \
157 "vram=${vram} " \
158 "omapfb.mode=dvi:${dvimode} " \
159 "omapfb.debug=y " \
160 "omapdss.def_disp=${defaultdisplay} " \
161 "root=${mmcroot} " \
162 "rootfstype=${mmcrootfstype}\0" \
163 "nandargs=setenv bootargs console=${console} " \
164 "mpurate=${mpurate} " \
165 "vram=${vram} " \
166 "omapfb.mode=dvi:${dvimode} " \
167 "omapfb.debug=y " \
168 "omapdss.def_disp=${defaultdisplay} " \
169 "root=${nandroot} " \
170 "rootfstype=${nandrootfstype}\0" \
Enric Balletbo i Serracffccee2013-08-07 17:53:18 +0200171 "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
Enric Balletbo i Serrad7cba702012-04-25 02:33:50 +0000172 "importbootenv=echo Importing environment from mmc ...; " \
173 "env import -t $loadaddr $filesize\0" \
Javier Martinez Canillas7a0155e2013-08-07 17:53:19 +0200174 "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
175 "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -0400176 "mmcboot=echo Booting from mmc ...; " \
177 "run mmcargs; " \
Enric Balletbo i Serracffccee2013-08-07 17:53:18 +0200178 "bootz ${loadaddr}\0" \
Javier Martinez Canillas7a0155e2013-08-07 17:53:19 +0200179 "mmcbootfdt=echo Booting with DT from mmc ...; " \
180 "bootz ${loadaddr} - ${dtbaddr}\0" \
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -0400181 "nandboot=echo Booting from onenand ...; " \
182 "run nandargs; " \
183 "onenand read ${loadaddr} 280000 400000; " \
Enric Balletbo i Serracffccee2013-08-07 17:53:18 +0200184 "bootz ${loadaddr}\0" \
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -0400185
186#define CONFIG_BOOTCOMMAND \
Andrew Bradforde1c7c8a2012-10-01 05:06:52 +0000187 "mmc dev ${mmcdev}; if mmc rescan; then " \
Enric Balletbo i Serrad7cba702012-04-25 02:33:50 +0000188 "echo SD/MMC found on device ${mmcdev};" \
189 "if run loadbootenv; then " \
190 "run importbootenv;" \
191 "fi;" \
192 "if test -n $uenvcmd; then " \
193 "echo Running uenvcmd ...;" \
194 "run uenvcmd;" \
195 "fi;" \
Enric Balletbo i Serracffccee2013-08-07 17:53:18 +0200196 "if run loadzimage; then " \
Javier Martinez Canillas7a0155e2013-08-07 17:53:19 +0200197 "if test -n $dtbfile; then " \
198 "if run loadfdt; then " \
199 "run mmcbootfdt;" \
200 "fi;" \
201 "fi;" \
Enric Balletbo i Serrad7cba702012-04-25 02:33:50 +0000202 "run mmcboot;" \
203 "fi;" \
204 "fi;" \
205 "run nandboot;" \
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400206
207#define CONFIG_AUTO_COMPLETE 1
208
209/*
210 * Miscellaneous configurable options
211 */
212#define CONFIG_SYS_LONGHELP /* undef to save memory */
213#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400214#define CONFIG_SYS_PROMPT "U-Boot # "
215#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
216/* Print Buffer Size */
217#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
218 sizeof(CONFIG_SYS_PROMPT) + 16)
219#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
220/* Boot Argument Buffer Size */
221#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
222
223#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
224 /* works on */
225#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
226 0x01F00000) /* 31MB */
227
228#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
229 /* load address */
230
231#define CONFIG_SYS_MONITOR_LEN (256 << 10)
232
233/*
234 * OMAP3 has 12 GP timers, they can be driven by the system clock
235 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
236 * This rate is divided by a local divisor.
237 */
238#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
239#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
240#define CONFIG_SYS_HZ 1000
241
242/*
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400243 * Physical Memory Map
244 *
245 */
246#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
247#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400248#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
249
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400250/*
251 * FLASH and environment organization
252 */
253
Javier Martinez Canillas758b7c62012-07-28 01:19:32 +0000254#ifdef CONFIG_BOOT_ONENAND
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400255#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
256
257#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
258
259#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
260
261#define CONFIG_ENV_IS_IN_ONENAND 1
262#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
263#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
Javier Martinez Canillas758b7c62012-07-28 01:19:32 +0000264#endif
265
266#ifdef CONFIG_BOOT_NAND
267#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
268#define CONFIG_NAND_OMAP_GPMC
269#define CONFIG_SYS_NAND_BASE NAND_BASE
270#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
271#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
272#define CONFIG_ENV_IS_IN_NAND 1
273#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
274#define CONFIG_ENV_ADDR NAND_ENV_OFFSET
275#define CONFIG_SYS_MAX_NAND_DEVICE 1
276#endif
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400277
278/*
279 * Size of malloc() pool
280 */
281#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400282
283/*
284 * SMSC911x Ethernet
285 */
286#if defined(CONFIG_CMD_NET)
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400287#define CONFIG_SMC911X
288#define CONFIG_SMC911X_32_BIT
289#define CONFIG_SMC911X_BASE 0x2C000000
290#endif /* (CONFIG_CMD_NET) */
291
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000292/*
293 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
294 * and older u-boot.bin with the new U-Boot SPL.
295 */
296#define CONFIG_SYS_TEXT_BASE 0x80008000
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400297#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Steve Sakomanb74d3b42010-10-27 05:04:30 -0700298#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
299#define CONFIG_SYS_INIT_RAM_SIZE 0x800
300#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
301 CONFIG_SYS_INIT_RAM_SIZE - \
302 GENERATED_GBL_DATA_SIZE)
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400303
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000304/* SPL */
305#define CONFIG_SPL
Tom Rini28591df2012-08-13 12:03:19 -0700306#define CONFIG_SPL_FRAMEWORK
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000307#define CONFIG_SPL_NAND_SIMPLE
308#define CONFIG_SPL_TEXT_BASE 0x40200800
309#define CONFIG_SPL_MAX_SIZE (54 * 1024)
310#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
311
312/* move malloc and bss high to prevent clashing with the main image */
313#define CONFIG_SYS_SPL_MALLOC_START 0x87000000
314#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
315#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
316#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
317
318/* MMC boot config */
319#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
320#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
321#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
322#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
323
Javier Martinez Canillas5a755952012-12-28 02:51:53 +0000324#define CONFIG_SPL_BOARD_INIT
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000325#define CONFIG_SPL_LIBCOMMON_SUPPORT
326#define CONFIG_SPL_LIBDISK_SUPPORT
327#define CONFIG_SPL_I2C_SUPPORT
328#define CONFIG_SPL_LIBGENERIC_SUPPORT
329#define CONFIG_SPL_MMC_SUPPORT
330#define CONFIG_SPL_FAT_SUPPORT
331#define CONFIG_SPL_SERIAL_SUPPORT
332
333#define CONFIG_SPL_POWER_SUPPORT
334#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
335
336#ifdef CONFIG_BOOT_ONENAND
337#define CONFIG_SPL_ONENAND_SUPPORT
338
339/* OneNAND boot config */
340#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000
341#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048
342#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000
343#define CONFIG_SPL_ONENAND_LOAD_SIZE \
344 (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
345
346#endif
347
348#ifdef CONFIG_BOOT_NAND
349#define CONFIG_SPL_NAND_SUPPORT
Scott Woodc352a0c2012-09-20 19:09:07 -0500350#define CONFIG_SPL_NAND_BASE
351#define CONFIG_SPL_NAND_DRIVERS
352#define CONFIG_SPL_NAND_ECC
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000353
354/* NAND boot config */
355#define CONFIG_SYS_NAND_5_ADDR_CYCLE
356#define CONFIG_SYS_NAND_PAGE_COUNT 64
357#define CONFIG_SYS_NAND_PAGE_SIZE 2048
358#define CONFIG_SYS_NAND_OOBSIZE 64
359#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
360#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
361#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
362 10, 11, 12, 13}
363#define CONFIG_SYS_NAND_ECCSIZE 512
364#define CONFIG_SYS_NAND_ECCBYTES 3
365#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
366#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
367#endif
368
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +0000369#endif /* __IGEP00X0_H */