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git01.mediatek.com / filogic / uboot / 49d30273b8fa6dd4c1dbfd1d164d1a2bbb472812 / . / arch / arm / dts / imx6qdl-dhcom-pdk2.dtsi
blob: d8772a98966e319e92b42aaeb57fb5bf790cb7a7 [file] [log] [blame]
Ludwig Zenz72352722019-07-02 14:49:47 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+)
2/*
3 * Copyright (C) 2015-2019 DH electronics GmbH
4 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
5 */
6
7#include "imx6qdl-dhcom.dtsi"
8
9/ {
10 chosen {
11 stdout-path = &uart1;
12 };
13
14 clk_ext_audio_codec: clock-codec {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <24000000>;
18 };
19
20 sound {
21 compatible = "fsl,imx-audio-sgtl5000";
22 model = "imx-sgtl5000";
23 ssi-controller = <&ssi1>;
24 audio-codec = <&sgtl5000>;
25 audio-routing =
26 "MIC_IN", "Mic Jack",
27 "Mic Jack", "Mic Bias",
28 "LINE_IN", "Line In Jack",
29 "Headphone Jack", "HP_OUT";
30 mux-int-port = <1>;
31 mux-ext-port = <3>;
32 };
33};
34
35&audmux {
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_audmux_ext>;
38 status = "okay";
39};
40
Christoph Niedermaier62b46de2021-11-28 03:53:18 +0100[diff] [blame]41/* 1G ethernet */
42/delete-node/ &ethphy0;
43&fec {
44 phy-mode = "rgmii";
45 phy-handle = <&ethphy7>;
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_enet_1G>;
48 status = "okay";
49
50 mdio {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 ethphy7: ethernet-phy@7 { /* KSZ 9021 */
55 compatible = "ethernet-phy-ieee802.3-c22";
56 interrupt-parent = <&gpio1>;
57 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
58 pinctrl-0 = <&pinctrl_ethphy7>;
59 pinctrl-names = "default";
60 reg = <7>;
61 reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
62 reset-assert-us = <1000>;
63 reset-deassert-us = <1000>;
64 rxc-skew-ps = <3000>;
65 rxd0-skew-ps = <0>;
66 rxd1-skew-ps = <0>;
67 rxd2-skew-ps = <0>;
68 rxd3-skew-ps = <0>;
69 txc-skew-ps = <3000>;
70 txd0-skew-ps = <0>;
71 txd1-skew-ps = <0>;
72 txd2-skew-ps = <0>;
73 txd3-skew-ps = <0>;
74 rxdv-skew-ps = <0>;
75 txen-skew-ps = <0>;
76 };
77 };
78};
79
Ludwig Zenz72352722019-07-02 14:49:47 +0200[diff] [blame]80&hdmi {
81 ddc-i2c-bus = <&i2c2>;
82 status = "okay";
83};
84
85&i2c2 {
86 sgtl5000: codec@a {
87 compatible = "fsl,sgtl5000";
88 reg = <0x0a>;
89 #sound-dai-cells = <0>;
90 clocks = <&clk_ext_audio_codec>;
91 VDDA-supply = <&reg_3p3v>;
92 VDDIO-supply = <&reg_3p3v>;
93 };
94};
95
96&iomuxc {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
99
100 pinctrl_hog: hog-grp {
101 fsl,pins = <
102 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0
103 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0
104 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0
105 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0
106 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0
107 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0
108 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0
109 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0
110 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0
111 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0
112 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0
113 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0
114 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0
115 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0
116 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0
117 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0
118 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0
119 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0
120 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0
121 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0
122 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0
123 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0
124 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0
125 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0
126 >;
127 };
128
129 pinctrl_audmux_ext: audmux-ext-grp {
130 fsl,pins = <
131 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
132 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
133 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
134 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
135 >;
136 };
137
138 pinctrl_enet_1G: enet-1G-grp {
139 fsl,pins = <
140 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
141 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
142 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
143 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
144 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
145 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
146 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
147 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
148 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
149 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
150 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
151 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
152 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
153 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
154 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
Christoph Niedermaier62b46de2021-11-28 03:53:18 +0100[diff] [blame]155 >;
156 };
157
158 pinctrl_ethphy7: ethphy7-grp {
159 fsl,pins = <
160 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */
161 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */
162 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */
Ludwig Zenz72352722019-07-02 14:49:47 +0200[diff] [blame]163 >;
164 };
165
166 pinctrl_pcie: pcie-grp {
167 fsl,pins = <
168 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1
169 >;
170 };
171};
172
173&pcie {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_pcie>;
176 reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
177 status = "okay";
178};
179
180&ssi1 {
181 status = "okay";
182};
183
184&usdhc3 {
185 status = "okay";
186};