blob: a04e7f98b9d9ec3b8e92550f381c69f111db1be0 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Galae1c09492010-07-15 16:49:03 -05002/*
ramneek mehresh3d339632012-04-18 19:39:53 +00003 * Copyright 2009-2012 Freescale Semiconductor, Inc.
Rajesh Bhagataec38012021-11-09 16:30:38 +05304 * Copyright 2020-2021 NXP
Kumar Galae1c09492010-07-15 16:49:03 -05005 */
6
7/*
8 * Corenet DS style board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Simon Glassfb64e362020-05-10 11:40:09 -060013#include <linux/stringify.h>
14
Kumar Galae1c09492010-07-15 16:49:03 -050015#include "../board/freescale/common/ics307_clk.h"
16
Shaohui Xie25a2b392011-03-16 10:10:32 +080017#ifdef CONFIG_RAMBOOT_PBL
Udit Agarwald2dd2f72019-11-07 16:11:39 +000018#ifdef CONFIG_NXP_ESBC
Shaohui Xie25a2b392011-03-16 10:10:32 +080019#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Miquel Raynald0935362019-10-03 19:50:03 +020021#ifdef CONFIG_MTD_RAW_NAND
Aneesh Bansale0f50152015-06-16 10:36:00 +053022#define CONFIG_RAMBOOT_NAND
23#endif
Aneesh Bansalb69061d2015-06-16 10:36:43 +053024#define CONFIG_BOOTSCRIPT_COPY_RAM
Aneesh Bansale0f50152015-06-16 10:36:00 +053025#else
26#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Shaohui Xie25a2b392011-03-16 10:10:32 +080028#endif
Aneesh Bansale0f50152015-06-16 10:36:00 +053029#endif
Shaohui Xie25a2b392011-03-16 10:10:32 +080030
Liu Gangb4611ee2012-08-09 05:10:03 +000031#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
Liu Gang1e084582012-03-08 00:33:18 +000032/* Set 1M boot space */
Liu Gangb4611ee2012-08-09 05:10:03 +000033#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
34#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
35 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
Liu Gang1e084582012-03-08 00:33:18 +000036#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Liu Gang1e084582012-03-08 00:33:18 +000037#endif
38
Kumar Galae1c09492010-07-15 16:49:03 -050039/* High Level Configuration Options */
Kumar Galae1c09492010-07-15 16:49:03 -050040#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Kumar Galae1c09492010-07-15 16:49:03 -050041
Kumar Galae727a362011-01-12 02:48:53 -060042#ifndef CONFIG_RESET_VECTOR_ADDRESS
43#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
44#endif
45
Kumar Galae1c09492010-07-15 16:49:03 -050046#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sunfe845072016-12-28 08:43:45 -080047#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Robert P. J. Daya8099812016-05-03 19:52:49 -040048#define CONFIG_PCIE1 /* PCIE controller 1 */
49#define CONFIG_PCIE2 /* PCIE controller 2 */
Kumar Galae1c09492010-07-15 16:49:03 -050050#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
Kumar Galae1c09492010-07-15 16:49:03 -050051
Shaohui Xiec6083892011-05-12 18:46:40 +080052#if defined(CONFIG_SPIFLASH)
Shaohui Xiec6083892011-05-12 18:46:40 +080053#elif defined(CONFIG_SDCARD)
Fabio Estevamae8c45e2012-01-11 09:20:50 +000054#define CONFIG_FSL_FIXED_MMC_LOCATION
Kumar Galae1c09492010-07-15 16:49:03 -050055#endif
56
57#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
Kumar Galae1c09492010-07-15 16:49:03 -050058
59/*
60 * These can be toggled for performance analysis, otherwise use default.
61 */
62#define CONFIG_SYS_CACHE_STASHING
63#define CONFIG_BACKSIDE_L2_CACHE
64#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
65#define CONFIG_BTB /* toggle branch predition */
Kumar Galae1c09492010-07-15 16:49:03 -050066#ifdef CONFIG_DDR_ECC
Kumar Galae1c09492010-07-15 16:49:03 -050067#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
68#endif
69
70#define CONFIG_ENABLE_36BIT_PHYS
71
York Sun18acc8b2010-09-28 15:20:36 -070072#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
Kumar Galae1c09492010-07-15 16:49:03 -050073
74/*
Shaohui Xie25a2b392011-03-16 10:10:32 +080075 * Config the L3 Cache as L3 SRAM
76 */
77#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
78#ifdef CONFIG_PHYS_64BIT
79#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
80#else
81#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
82#endif
83#define CONFIG_SYS_L3_SIZE (1024 << 10)
84#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
85
Kumar Galae1c09492010-07-15 16:49:03 -050086#ifdef CONFIG_PHYS_64BIT
87#define CONFIG_SYS_DCSRBAR 0xf0000000
88#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
89#endif
90
91/* EEPROM */
Kumar Galae1c09492010-07-15 16:49:03 -050092#define CONFIG_SYS_I2C_EEPROM_NXID
93#define CONFIG_SYS_EEPROM_BUS_NUM 0
Kumar Galae1c09492010-07-15 16:49:03 -050094
95/*
96 * DDR Setup
97 */
98#define CONFIG_VERY_BIG_RAM
99#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
100#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
101
102#define CONFIG_DIMM_SLOTS_PER_CTLR 1
york0b2bb6d2010-07-02 22:25:59 +0000103#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
Kumar Galae1c09492010-07-15 16:49:03 -0500104
Kumar Galae1c09492010-07-15 16:49:03 -0500105#define CONFIG_SYS_SPD_BUS_NUM 1
106#define SPD_EEPROM_ADDRESS1 0x51
107#define SPD_EEPROM_ADDRESS2 0x52
Kumar Galae38209e2011-02-09 02:00:08 +0000108#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
York Sun269c7eb2010-10-18 13:46:49 -0700109#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
Kumar Galae1c09492010-07-15 16:49:03 -0500110
111/*
112 * Local Bus Definitions
113 */
114
115/* Set the local bus clock 1/8 of platform clock */
116#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
117
118#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
119#ifdef CONFIG_PHYS_64BIT
120#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
121#else
122#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
123#endif
124
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800125#define CONFIG_SYS_FLASH_BR_PRELIM \
Timur Tabib56570c2012-07-06 07:39:26 +0000126 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
Shaohui Xiee04e16b2011-05-09 16:53:51 +0800127 | BR_PS_16 | BR_V)
128#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
Kumar Galae1c09492010-07-15 16:49:03 -0500129 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
130
Kumar Galae1c09492010-07-15 16:49:03 -0500131#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
132#ifdef CONFIG_PHYS_64BIT
133#define PIXIS_BASE_PHYS 0xfffdf0000ull
134#else
135#define PIXIS_BASE_PHYS PIXIS_BASE
136#endif
137
Kumar Galae1c09492010-07-15 16:49:03 -0500138#define PIXIS_LBMAP_SWITCH 7
139#define PIXIS_LBMAP_MASK 0xf0
140#define PIXIS_LBMAP_SHIFT 4
141#define PIXIS_LBMAP_ALTBANK 0x40
142
143#define CONFIG_SYS_FLASH_QUIET_TEST
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200144#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Kumar Galae1c09492010-07-15 16:49:03 -0500145
146#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
147#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
148#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
149#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
150
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200151#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kumar Galae1c09492010-07-15 16:49:03 -0500152
Shaohui Xie25a2b392011-03-16 10:10:32 +0800153#if defined(CONFIG_RAMBOOT_PBL)
154#define CONFIG_SYS_RAMBOOT
155#endif
156
Kumar Galae38209e2011-02-09 02:00:08 +0000157/* Nand Flash */
Kumar Galae38209e2011-02-09 02:00:08 +0000158#ifdef CONFIG_NAND_FSL_ELBC
159#define CONFIG_SYS_NAND_BASE 0xffa00000
160#ifdef CONFIG_PHYS_64BIT
161#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
162#else
163#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
164#endif
165
166#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
167#define CONFIG_SYS_MAX_NAND_DEVICE 1
Kumar Galae38209e2011-02-09 02:00:08 +0000168
169/* NAND flash config */
170#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
171 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
172 | BR_PS_8 /* Port Size = 8 bit */ \
173 | BR_MS_FCM /* MSEL = FCM */ \
174 | BR_V) /* valid */
175#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
176 | OR_FCM_PGS /* Large Page*/ \
177 | OR_FCM_CSCT \
178 | OR_FCM_CST \
179 | OR_FCM_CHT \
180 | OR_FCM_SCY_1 \
181 | OR_FCM_TRLX \
182 | OR_FCM_EHTR)
Kumar Galad0af3b92011-08-31 09:50:13 -0500183#endif /* CONFIG_NAND_FSL_ELBC */
Kumar Galae38209e2011-02-09 02:00:08 +0000184
Kumar Galae1c09492010-07-15 16:49:03 -0500185#define CONFIG_SYS_FLASH_EMPTY_INFO
Kumar Galae1c09492010-07-15 16:49:03 -0500186#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
187
Kumar Galae1c09492010-07-15 16:49:03 -0500188#define CONFIG_HWCONFIG
189
190/* define to use L1 as initial stack */
191#define CONFIG_L1_INIT_RAM
192#define CONFIG_SYS_INIT_RAM_LOCK
193#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
194#ifdef CONFIG_PHYS_64BIT
195#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
196#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
197/* The assembler doesn't like typecast */
198#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
199 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
200 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
201#else
202#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
203#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
204#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
205#endif
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200206#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Galae1c09492010-07-15 16:49:03 -0500207
Wolfgang Denk0191e472010-10-26 14:34:52 +0200208#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kumar Galae1c09492010-07-15 16:49:03 -0500209#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
210
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530211#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Kumar Galae1c09492010-07-15 16:49:03 -0500212
213/* Serial Port - controlled on board with jumper J8
214 * open - index 2
215 * shorted - index 1
216 */
Kumar Galae1c09492010-07-15 16:49:03 -0500217#define CONFIG_SYS_NS16550_SERIAL
218#define CONFIG_SYS_NS16550_REG_SIZE 1
219#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
220
221#define CONFIG_SYS_BAUDRATE_TABLE \
222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
223
224#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
225#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
226#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
227#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
228
Kumar Galae1c09492010-07-15 16:49:03 -0500229/* I2C */
Kumar Galae1c09492010-07-15 16:49:03 -0500230
231/*
232 * RapidIO
233 */
Kumar Gala8975d7a2010-12-30 12:09:53 -0600234#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500235#ifdef CONFIG_PHYS_64BIT
Kumar Gala8975d7a2010-12-30 12:09:53 -0600236#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500237#else
Kumar Gala8975d7a2010-12-30 12:09:53 -0600238#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500239#endif
Kumar Gala8975d7a2010-12-30 12:09:53 -0600240#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
Kumar Galae1c09492010-07-15 16:49:03 -0500241
Kumar Gala8975d7a2010-12-30 12:09:53 -0600242#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500243#ifdef CONFIG_PHYS_64BIT
Kumar Gala8975d7a2010-12-30 12:09:53 -0600244#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500245#else
Kumar Gala8975d7a2010-12-30 12:09:53 -0600246#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500247#endif
Kumar Gala8975d7a2010-12-30 12:09:53 -0600248#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
Kumar Galae1c09492010-07-15 16:49:03 -0500249
250/*
Liu Gang4cc85322012-03-08 00:33:17 +0000251 * for slave u-boot IMAGE instored in master memory space,
252 * PHYS must be aligned based on the SIZE
253 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800254#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
255#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
256#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
257#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Liu Gang85bcd732012-03-08 00:33:20 +0000258/*
Liu Gangd7b17a92012-08-09 05:09:59 +0000259 * for slave UCODE and ENV instored in master memory space,
Liu Gang85bcd732012-03-08 00:33:20 +0000260 * PHYS must be aligned based on the SIZE
261 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800262#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Liu Gang99e0c292012-08-09 05:10:02 +0000263#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
264#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
Liu Gangd7b17a92012-08-09 05:09:59 +0000265
Liu Gangf420aa92012-03-08 00:33:21 +0000266/* slave core release by master*/
Liu Gang99e0c292012-08-09 05:10:02 +0000267#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
268#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
Liu Gang4cc85322012-03-08 00:33:17 +0000269
270/*
Liu Gangb4611ee2012-08-09 05:10:03 +0000271 * SRIO_PCIE_BOOT - SLAVE
Liu Gang1e084582012-03-08 00:33:18 +0000272 */
Liu Gangb4611ee2012-08-09 05:10:03 +0000273#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
274#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
275#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
276 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
Liu Gang1e084582012-03-08 00:33:18 +0000277#endif
278
279/*
Shaohui Xie58649792011-05-12 18:46:14 +0800280 * eSPI - Enhanced SPI
281 */
Shaohui Xie58649792011-05-12 18:46:14 +0800282
283/*
Kumar Galae1c09492010-07-15 16:49:03 -0500284 * General PCI
285 * Memory space is mapped 1-1, but I/O space must start from 0.
286 */
287
288/* controller 1, direct to uli, tgtid 3, Base address 20000 */
289#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Kumar Galae1c09492010-07-15 16:49:03 -0500290#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500291#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
Kumar Galae1c09492010-07-15 16:49:03 -0500292#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500293
294/* controller 2, Slot 2, tgtid 2, Base address 201000 */
295#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500296#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500297#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
Kumar Galae1c09492010-07-15 16:49:03 -0500298#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500299
300/* controller 3, Slot 1, tgtid 1, Base address 202000 */
Trübenbach, Ralfd8ec2c02011-04-20 13:04:47 +0000301#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
Kumar Galae1c09492010-07-15 16:49:03 -0500302#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500303#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
Kumar Galae1c09492010-07-15 16:49:03 -0500304#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
Kumar Galae1c09492010-07-15 16:49:03 -0500305
Kumar Gala67a6dfe2010-07-09 09:12:18 -0500306/* controller 4, Base address 203000 */
Kumar Gala67a6dfe2010-07-09 09:12:18 -0500307#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
Kumar Gala67a6dfe2010-07-09 09:12:18 -0500308#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
Kumar Gala67a6dfe2010-07-09 09:12:18 -0500309
Kumar Galae1c09492010-07-15 16:49:03 -0500310/* Qman/Bman */
311#define CONFIG_SYS_BMAN_NUM_PORTALS 10
312#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
313#ifdef CONFIG_PHYS_64BIT
314#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
315#else
316#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
317#endif
318#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500319#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
320#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
321#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
322#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
323#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
324 CONFIG_SYS_BMAN_CENA_SIZE)
325#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
326#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Kumar Galae1c09492010-07-15 16:49:03 -0500327#define CONFIG_SYS_QMAN_NUM_PORTALS 10
328#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
329#ifdef CONFIG_PHYS_64BIT
330#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
331#else
332#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
333#endif
334#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500335#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
336#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
337#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
338#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
339#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
340 CONFIG_SYS_QMAN_CENA_SIZE)
341#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
342#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Kumar Galae1c09492010-07-15 16:49:03 -0500343
344#define CONFIG_SYS_DPAA_FMAN
345#define CONFIG_SYS_DPAA_PME
Timur Tabi275f4bb2011-11-22 09:21:25 -0600346#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
Kumar Galae1c09492010-07-15 16:49:03 -0500347
Kumar Galae1c09492010-07-15 16:49:03 -0500348#ifdef CONFIG_PCI
Kumar Galae1c09492010-07-15 16:49:03 -0500349#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Kumar Galae1c09492010-07-15 16:49:03 -0500350#endif /* CONFIG_PCI */
351
352/* SATA */
353#ifdef CONFIG_FSL_SATA_V2
Kumar Galae1c09492010-07-15 16:49:03 -0500354#define CONFIG_SYS_SATA_MAX_DEVICE 2
355#define CONFIG_SATA1
356#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
357#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
358#define CONFIG_SATA2
359#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
360#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
361
362#define CONFIG_LBA48
Kumar Galae1c09492010-07-15 16:49:03 -0500363#endif
364
365#ifdef CONFIG_FMAN_ENET
366#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
367#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
368#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
369#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
370#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
371
Kumar Galae1c09492010-07-15 16:49:03 -0500372#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
373#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
374#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
375#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
376#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
Kumar Galae1c09492010-07-15 16:49:03 -0500377
378#define CONFIG_SYS_TBIPA_VALUE 8
Kumar Galae1c09492010-07-15 16:49:03 -0500379#define CONFIG_ETHPRIME "FM1@DTSEC1"
Kumar Galae1c09492010-07-15 16:49:03 -0500380#endif
381
382/*
383 * Environment
384 */
Kumar Galae1c09492010-07-15 16:49:03 -0500385#define CONFIG_LOADS_ECHO /* echo on for serial download */
386#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
387
388/*
Kumar Galae1c09492010-07-15 16:49:03 -0500389* USB
390*/
ramneek mehresh3d339632012-04-18 19:39:53 +0000391#define CONFIG_HAS_FSL_DR_USB
392#define CONFIG_HAS_FSL_MPH_USB
393
394#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
Kumar Galae1c09492010-07-15 16:49:03 -0500395#define CONFIG_USB_EHCI_FSL
396#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
ramneek mehresh3d339632012-04-18 19:39:53 +0000397#endif
Kumar Galae1c09492010-07-15 16:49:03 -0500398
Kumar Galae1c09492010-07-15 16:49:03 -0500399#ifdef CONFIG_MMC
Kumar Galae1c09492010-07-15 16:49:03 -0500400#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
401#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Kumar Galae1c09492010-07-15 16:49:03 -0500402#endif
403
404/*
405 * Miscellaneous configurable options
406 */
Kumar Galae1c09492010-07-15 16:49:03 -0500407
408/*
409 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500410 * have to be in the first 64 MB of memory, since this is
Kumar Galae1c09492010-07-15 16:49:03 -0500411 * the maximum mapped by the Linux kernel during initialization.
412 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500413#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
414#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Galae1c09492010-07-15 16:49:03 -0500415
Kumar Galae1c09492010-07-15 16:49:03 -0500416/*
417 * Environment Configuration
418 */
Joe Hershberger257ff782011-10-13 13:03:47 +0000419#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000420#define CONFIG_BOOTFILE "uImage"
Kumar Galae1c09492010-07-15 16:49:03 -0500421#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
422
York Sund1bb6022016-11-18 11:26:09 -0800423#ifdef CONFIG_TARGET_P4080DS
Ramneek Mehresha0cce272011-06-07 10:10:43 +0000424#define __USB_PHY_TYPE ulpi
425#else
426#define __USB_PHY_TYPE utmi
427#endif
428
Kumar Galae1c09492010-07-15 16:49:03 -0500429#define CONFIG_EXTRA_ENV_SETTINGS \
Emil Medveb250d372010-08-31 22:57:43 -0500430 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
Ramneek Mehresha0cce272011-06-07 10:10:43 +0000431 "bank_intlv=cs0_cs1;" \
ramneek mehresh1b57b002013-09-10 17:37:45 +0530432 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
433 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
Kumar Galae1c09492010-07-15 16:49:03 -0500434 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200435 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
436 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Emil Medveb250d372010-08-31 22:57:43 -0500437 "tftpflash=tftpboot $loadaddr $uboot && " \
438 "protect off $ubootaddr +$filesize && " \
439 "erase $ubootaddr +$filesize && " \
440 "cp.b $loadaddr $ubootaddr $filesize && " \
441 "protect on $ubootaddr +$filesize && " \
442 "cmp.b $loadaddr $ubootaddr $filesize\0" \
Kumar Galae1c09492010-07-15 16:49:03 -0500443 "consoledev=ttyS0\0" \
444 "ramdiskaddr=2000000\0" \
445 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500446 "fdtaddr=1e00000\0" \
Kumar Galae1c09492010-07-15 16:49:03 -0500447 "fdtfile=p4080ds/p4080ds.dtb\0" \
Kim Phillips1dedccc2014-05-14 19:33:45 -0500448 "bdev=sda3\0"
Kumar Galae1c09492010-07-15 16:49:03 -0500449
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000450#include <asm/fsl_secure_boot.h>
Ruchika Gupta8ca8d822010-12-15 17:02:08 +0000451
Kumar Galae1c09492010-07-15 16:49:03 -0500452#endif /* __CONFIG_H */