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Bo Shen42aafb32012-07-05 17:21:46 +00001/*
2 * Copyright (C) 2012 Atmel Corporation
3 *
4 * Configuation settings for the AT91SAM9X5EK board.
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Bo Shen42aafb32012-07-05 17:21:46 +00007 */
8
9#ifndef __CONFIG_H__
10#define __CONFIG_H__
11
12#include <asm/hardware.h>
13
Bo Shen337a2d82013-08-13 14:50:49 +080014#define CONFIG_SYS_TEXT_BASE 0x26f00000
15
Bo Shen42aafb32012-07-05 17:21:46 +000016/* ARM asynchronous clock */
17#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
18#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
Bo Shen42aafb32012-07-05 17:21:46 +000019
20#define CONFIG_AT91SAM9X5EK
Bo Shen42aafb32012-07-05 17:21:46 +000021
Bo Shen42aafb32012-07-05 17:21:46 +000022#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23#define CONFIG_SETUP_MEMORY_TAGS
24#define CONFIG_INITRD_TAG
25#define CONFIG_SKIP_LOWLEVEL_INIT
Bo Shen42aafb32012-07-05 17:21:46 +000026
27/* general purpose I/O */
28#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
29#define CONFIG_AT91_GPIO
30
31/* serial console */
32#define CONFIG_ATMEL_USART
33#define CONFIG_USART_BASE ATMEL_BASE_DBGU
34#define CONFIG_USART_ID ATMEL_ID_SYS
35
36/* LCD */
Bo Shen42aafb32012-07-05 17:21:46 +000037#define LCD_BPP LCD_COLOR16
38#define LCD_OUTPUT_BPP 24
39#define CONFIG_LCD_LOGO
Bo Shen42aafb32012-07-05 17:21:46 +000040#define CONFIG_LCD_INFO
41#define CONFIG_LCD_INFO_BELOW_LOGO
42#define CONFIG_SYS_WHITE_ON_BLACK
43#define CONFIG_ATMEL_HLCD
44#define CONFIG_ATMEL_LCD_RGB565
Bo Shen42aafb32012-07-05 17:21:46 +000045
Bo Shen42aafb32012-07-05 17:21:46 +000046
47/*
48 * BOOTP options
49 */
50#define CONFIG_BOOTP_BOOTFILESIZE
51#define CONFIG_BOOTP_BOOTPATH
52#define CONFIG_BOOTP_GATEWAY
53#define CONFIG_BOOTP_HOSTNAME
54
Bo Shen963a2b12013-12-10 16:14:02 +080055/* no NOR flash */
56#define CONFIG_SYS_NO_FLASH
57
Bo Shen42aafb32012-07-05 17:21:46 +000058/*
59 * Command line configuration.
60 */
Bo Shen42aafb32012-07-05 17:21:46 +000061#define CONFIG_CMD_NAND
Richard Genoud1e34e832012-11-29 23:18:34 +000062
63/*
64 * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
65 * NB: in this case, USB 1.1 devices won't be recognized.
66 */
67
Bo Shen42aafb32012-07-05 17:21:46 +000068/* SDRAM */
69#define CONFIG_NR_DRAM_BANKS 1
70#define CONFIG_SYS_SDRAM_BASE 0x20000000
71#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
72
73#define CONFIG_SYS_INIT_SP_ADDR \
74 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
75
76/* DataFlash */
Bo Shen4a73e582012-08-19 20:32:24 +000077#ifdef CONFIG_CMD_SF
78#define CONFIG_ATMEL_SPI
Bo Shen4a73e582012-08-19 20:32:24 +000079#define CONFIG_SF_DEFAULT_SPEED 30000000
Bo Shen42aafb32012-07-05 17:21:46 +000080#endif
81
Bo Shen42aafb32012-07-05 17:21:46 +000082/* NAND flash */
83#ifdef CONFIG_CMD_NAND
84#define CONFIG_NAND_ATMEL
85#define CONFIG_SYS_MAX_NAND_DEVICE 1
86#define CONFIG_SYS_NAND_BASE 0x40000000
87#define CONFIG_SYS_NAND_DBW_8 1
88/* our ALE is AD21 */
89#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
90/* our CLE is AD22 */
91#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
92#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
93#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
94
Wu, Joshdd359a12012-08-23 00:05:38 +000095/* PMECC & PMERRLOC */
96#define CONFIG_ATMEL_NAND_HWECC 1
97#define CONFIG_ATMEL_NAND_HW_PMECC 1
98#define CONFIG_PMECC_CAP 2
99#define CONFIG_PMECC_SECTOR_SIZE 512
Wu, Joshdd359a12012-08-23 00:05:38 +0000100
Bo Shen591ef582013-06-26 10:48:53 +0800101#define CONFIG_CMD_NAND_TRIMFFS
102
Bo Shen42aafb32012-07-05 17:21:46 +0000103#define CONFIG_MTD_DEVICE
104#define CONFIG_CMD_MTDPARTS
105#define CONFIG_MTD_PARTITIONS
106#define CONFIG_RBTREE
107#define CONFIG_LZO
Bo Shen42aafb32012-07-05 17:21:46 +0000108#define CONFIG_CMD_UBIFS
109#endif
110
Wu, Joshe32c6612012-09-13 22:22:05 +0000111/* MMC */
112#ifdef CONFIG_CMD_MMC
Wu, Joshe32c6612012-09-13 22:22:05 +0000113#define CONFIG_GENERIC_MMC
114#define CONFIG_GENERIC_ATMEL_MCI
Richard Genoudfa2dbe72012-11-29 23:18:33 +0000115#endif
116
Bo Shen42aafb32012-07-05 17:21:46 +0000117/* Ethernet */
118#define CONFIG_MACB
119#define CONFIG_RMII
120#define CONFIG_NET_RETRY_COUNT 20
121#define CONFIG_MACB_SEARCH_PHY
122
Richard Genoud1e34e832012-11-29 23:18:34 +0000123/* USB */
124#ifdef CONFIG_CMD_USB
125#ifdef CONFIG_USB_EHCI
126#define CONFIG_USB_EHCI_ATMEL
127#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
128#else
Bo Shen4a985df2013-10-21 16:14:00 +0800129#define CONFIG_USB_ATMEL
130#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Richard Genoud1e34e832012-11-29 23:18:34 +0000131#define CONFIG_USB_OHCI_NEW
132#define CONFIG_SYS_USB_OHCI_CPU_INIT
133#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
134#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
135#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
136#endif
Richard Genoud1e34e832012-11-29 23:18:34 +0000137#endif
138
Bo Shen42aafb32012-07-05 17:21:46 +0000139#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
140
141#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
142#define CONFIG_SYS_MEMTEST_END 0x26e00000
143
144#ifdef CONFIG_SYS_USE_NANDFLASH
145/* bootstrap + u-boot + env + linux in nandflash */
146#define CONFIG_ENV_IS_IN_NAND
147#define CONFIG_ENV_OFFSET 0xc0000
148#define CONFIG_ENV_OFFSET_REDUND 0x100000
149#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
150#define CONFIG_BOOTCOMMAND "nand read " \
151 "0x22000000 0x200000 0x300000; " \
152 "bootm 0x22000000"
Wu, Josh9d681892012-11-02 00:17:27 +0000153#elif defined(CONFIG_SYS_USE_SPIFLASH)
Bo Shen4a73e582012-08-19 20:32:24 +0000154/* bootstrap + u-boot + env + linux in spi flash */
155#define CONFIG_ENV_IS_IN_SPI_FLASH
156#define CONFIG_ENV_OFFSET 0x5000
157#define CONFIG_ENV_SIZE 0x3000
158#define CONFIG_ENV_SECT_SIZE 0x1000
159#define CONFIG_ENV_SPI_MAX_HZ 30000000
160#define CONFIG_BOOTCOMMAND "sf probe 0; " \
161 "sf read 0x22000000 0x100000 0x300000; " \
162 "bootm 0x22000000"
Bo Shen0a9f8ac2012-12-06 21:37:04 +0000163#elif defined(CONFIG_SYS_USE_DATAFLASH)
164/* bootstrap + u-boot + env + linux in data flash */
165#define CONFIG_ENV_IS_IN_SPI_FLASH
166#define CONFIG_ENV_OFFSET 0x4200
167#define CONFIG_ENV_SIZE 0x4200
168#define CONFIG_ENV_SECT_SIZE 0x210
169#define CONFIG_ENV_SPI_MAX_HZ 30000000
170#define CONFIG_BOOTCOMMAND "sf probe 0; " \
171 "sf read 0x22000000 0x84000 0x294000; " \
172 "bootm 0x22000000"
Wu, Josh9d681892012-11-02 00:17:27 +0000173#else /* CONFIG_SYS_USE_MMC */
174/* bootstrap + u-boot + env + linux in mmc */
Wu, Joshdf0ef742015-01-20 10:33:33 +0800175#define CONFIG_ENV_IS_IN_FAT
176#define CONFIG_FAT_WRITE
177#define FAT_ENV_INTERFACE "mmc"
178#define FAT_ENV_FILE "uboot.env"
179#define FAT_ENV_DEVICE_AND_PART "0"
180#define CONFIG_ENV_SIZE 0x4000
Bo Shen42aafb32012-07-05 17:21:46 +0000181#endif
182
Wu, Josh9d681892012-11-02 00:17:27 +0000183#ifdef CONFIG_SYS_USE_MMC
Bo Shen42aafb32012-07-05 17:21:46 +0000184#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \
185 "mtdparts=atmel_nand:" \
186 "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
Wu, Josh9d681892012-11-02 00:17:27 +0000187 "root=/dev/mmcblk0p2 " \
188 "rw rootfstype=ext4 rootwait"
189#else
Bo Shena8fd0632013-02-20 00:16:25 +0000190#define CONFIG_BOOTARGS \
191 "console=ttyS0,115200 earlyprintk " \
192 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
193 "256k(env),256k(env_redundant),256k(spare)," \
194 "512k(dtb),6M(kernel)ro,-(rootfs) " \
195 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
Wu, Josh9d681892012-11-02 00:17:27 +0000196#endif
Bo Shen42aafb32012-07-05 17:21:46 +0000197
198#define CONFIG_BAUDRATE 115200
199
Bo Shen42aafb32012-07-05 17:21:46 +0000200#define CONFIG_SYS_CBSIZE 256
201#define CONFIG_SYS_MAXARGS 16
Bo Shen42aafb32012-07-05 17:21:46 +0000202#define CONFIG_SYS_LONGHELP
203#define CONFIG_CMDLINE_EDITING
204#define CONFIG_AUTO_COMPLETE
Bo Shen42aafb32012-07-05 17:21:46 +0000205
206/*
207 * Size of malloc() pool
208 */
209#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
210
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800211/* SPL */
212#define CONFIG_SPL_FRAMEWORK
213#define CONFIG_SPL_TEXT_BASE 0x300000
214#define CONFIG_SPL_MAX_SIZE 0x6000
215#define CONFIG_SPL_STACK 0x308000
216
217#define CONFIG_SPL_BSS_START_ADDR 0x20000000
218#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
219#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
220#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
221
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800222#define CONFIG_SPL_BOARD_INIT
223#define CONFIG_SYS_MONITOR_LEN (512 << 10)
224
225#define CONFIG_SYS_MASTER_CLOCK 132096000
226#define CONFIG_SYS_AT91_PLLA 0x20c73f03
227#define CONFIG_SYS_MCKR 0x1301
228#define CONFIG_SYS_MCKR_CSS 0x1302
229
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800230#ifdef CONFIG_SYS_USE_MMC
231#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800232#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
233#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800234
235#elif CONFIG_SYS_USE_NANDFLASH
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800236#define CONFIG_SPL_NAND_DRIVERS
237#define CONFIG_SPL_NAND_BASE
238#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
239#define CONFIG_SYS_NAND_5_ADDR_CYCLE
240#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
241#define CONFIG_SYS_NAND_PAGE_COUNT 64
242#define CONFIG_SYS_NAND_OOBSIZE 64
243#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
244#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
245#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
246
247#elif CONFIG_SYS_USE_SPIFLASH
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800248#define CONFIG_SPL_SPI_LOAD
249#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
250
251#endif
252
Bo Shen42aafb32012-07-05 17:21:46 +0000253#endif