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git01.mediatek.com / filogic / uboot / 47443370b121224815c74455c1d4db00b5a34437 / . / arch / arm / dts / imx8mm-beacon-kit-u-boot.dtsi
blob: 00abbeb22fe12908083db69494bc7607d25e2ff8 [file] [log] [blame]
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]8/ {
Adam Ford3a120e02023-02-01 19:58:40 -0600[diff] [blame]9 aliases {
10 spi0 = &flexspi;
11 };
12
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]13 wdt-reboot {
14 compatible = "wdt-reboot";
15 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]16 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]17 };
18};
19
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]20&aips4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]22};
23
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]24&reg_usdhc2_vmmc {
25 u-boot,off-on-delay-us = <20000>;
26};
27
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]28&fec1 {
29 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
30};
31
32&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]34};
35
36&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]38};
39
40&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]42};
43
44&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]46};
47
48&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]50};
51
52&pca6416_0 {
53 compatible = "ti,tca6416";
54};
55
56&pca6416_1 {
57 compatible = "ti,tca6416";
58};
59
60&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]62};
63
64&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]66};
67
68&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]70};
71
72&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]74};
75
76&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]78};
79
80&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]82};
83
Peng Fan28b60202022-06-11 20:21:02 +0800[diff] [blame]84&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Peng Fan28b60202022-06-11 20:21:02 +0800[diff] [blame]86};
87
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]88&reg_usbotg1 {
89
90};
91
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]92&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]94};
95
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]96&usbmisc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]98};
99
Adam Ford9191c272022-01-22 12:27:34 -0600[diff] [blame]100&usbotg1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]102};
103
104&usbphynop1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Adam Ford9191c272022-01-22 12:27:34 -0600[diff] [blame]106};
107
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]108&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]110};
111
112&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]114};
115
116&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]118};
119
120&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]122};
123
124&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]126};
127
128&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]130};