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git01.mediatek.com / filogic / uboot / d3a98cb671f08af821b3b046564783d649736c18 / . / arch / arm / dts / imx8mm-beacon-kit-u-boot.dtsi
blob: fd0061f00fd43311624021aac9f37ae945494248 [file] [log] [blame]
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]8/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]12 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]13 };
14};
15
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]16&aips4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]17 bootph-pre-ram;
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]18};
19
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]20&reg_usdhc2_vmmc {
21 u-boot,off-on-delay-us = <20000>;
22};
23
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]24&fec1 {
25 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
26};
27
28&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]29 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]30};
31
32&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]33 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]34};
35
36&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]37 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]38};
39
40&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]41 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]42};
43
44&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]45 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]46};
47
48&pca6416_0 {
49 compatible = "ti,tca6416";
50};
51
52&pca6416_1 {
53 compatible = "ti,tca6416";
54};
55
56&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]57 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]58};
59
60&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]61 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]62};
63
64&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]65 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]66};
67
68&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]69 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]70};
71
72&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]73 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]74};
75
76&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]77 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]78};
79
Peng Fan28b60202022-06-11 20:21:02 +0800[diff] [blame]80&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]81 bootph-pre-ram;
Peng Fan28b60202022-06-11 20:21:02 +0800[diff] [blame]82};
83
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]84&reg_usbotg1 {
85
86};
87
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]88&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]89 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]90};
91
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]92&usbmisc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]93 bootph-pre-ram;
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]94};
95
Adam Ford9191c272022-01-22 12:27:34 -0600[diff] [blame]96&usbotg1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]97 bootph-pre-ram;
Adam Ford2cc246a2022-10-22 09:28:23 -0500[diff] [blame]98};
99
100&usbphynop1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]101 bootph-pre-ram;
Adam Ford9191c272022-01-22 12:27:34 -0600[diff] [blame]102};
103
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]104&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]105 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]106};
107
108&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]109 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]110};
111
112&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]113 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]114};
115
116&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]117 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]118};
119
120&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]121 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]122};
123
124&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]125 bootph-pre-ram;
Adam Ford14879032020-05-03 08:11:33 -0500[diff] [blame]126};